技术领域

Data Converters

279 篇相关论文 (2008–2026)

ISSCC 2026 Session 32 Data Converters
A 103.9dB-SFDR 83.8dB-SNDR 3MHz-BW Multi-Bit Quadratic-Exponential Noise-Coupled IDSM with High Tolerance to DAC Non-Linearity
Zhensheng Li1,2, Biao Wang3, Mingqiang Guo1, Rui P. Martins1, Sai-Weng Sin1
Abstract This paper presents a quadratic-exponential noise-coupled (NC) IDSM to achieve a quantization noise shaping effect greater than 4th order with OSR 22, while having high tolerance to DAC non-linearity and a small
University of Macau, Macau, China, 2UM Hetao IC Research Institute, Sh
ISSCC 2026 Session 32 Data Converters
An 85.1dB-SNDR 8MS/s Incremental Pipeline ADC with Dual-Residue-Assisted Exponential Quantization
Zongnan Wang, Bingrui Li, Haoyang Luo, Chenyuan Chu, Jiachang Yang, Yuan Wang, Xiyuan Tang
Abstract This paper presents an incremental pipeline ADC with dual-residue architecture. An exponential ΔΣ loop is proposed to directly quantize the residue, replacing conventional interpolators that are complex and less
Peking University, Beijing, China
ISSCC 2026 Session 32 Data Converters
A PVT-Robust Frequency-Scalable Fully Dynamic ΔΣ ADC with Bottom-Plate Level Shift
Tohru Kaneko1, Hideaki Ishida1, Yuzuru Yamaki1, Satoshi Takehara1, Un-Ku Moon2
Abstract A fully dynamic calibration-free ΔΣ ADC using capacitive-degeneration integrators with bottom-plate level shift (BPLS) is presented. BPLS samples negative charge to reduce threshold-voltage dependence, improve s
Asahi Kasei Microdevices, Yokohama, Japan, 2Oregon State University, C
ISSCC 2026 Session 32 Data Converters
A 98.5dB-SNDR 250kHz-BW 1V-Supply Continuous-Time Zoom ADC with Smart-Tracking and Floating-Tail-Resistor Linearized Gm-C Loop Filter
Chaoyang Xing, Yilu Cui, Sining Pan, Yi Zhong, Nan Sun, Lu Jie
Abstract This paper presents a 98.5dB SNDR, 250kHz bandwidth CT incremental Zoom ADC. The design features a chopped capacitive front-end, Gm-C residue integrator, and 10b SAR ADC. A smart-tracking (ST) technique with dyn
Tsinghua University, Beijing, China
ISSCC 2026 Session 11 Data Converters
A 14b 20GS/s RF-Sampling DAC Achieving 70.4dBc IMD3 up to 8.9GHz
Hao Luo*, Zhijun Long*, Wentao Zhu, Haowei Lu, Yushen Fu, Mingqian Lei, Cheng Wang, Xiaoge Zhu, Yumei Diao, Haipeng Zhu,
RF-sampling DAC. By introducing a switch driver with process-and-temperature-adaptive (PT-adaptive) level shifting and enhanced low-crosspoint control, the DAC demonstrates an IMD3 of 70.8dBc at 7.2GHz and 16Gs/s, and a
Yi Yang, Xinli Geng, Keqing Ouyang Sanechips Technology, Shenzhen, Chi
ISSCC 2026 Session 11 Data Converters
A 12b 12GS/s Two-Way Interleaved Pipeline ADC with Integrated Broadband RF VGA in 5nm
Haiyang Zhu1, Larry Singer1, Ron Kapusta1, Dan Kelly1, Tao Pan1, Mike Hensley2, Scott Bardsley3, Chris Dillon3, Daniel R
Chen-Kai Hsu1, Zhao Li6, Janet Brunsilius4, Enrique Alvarez-Fontecilla4, Robert Bishop1, Paul Wilkins1, Hassan L’Bahy1, Adalberto Cantoni1, Nuo Zhang1, Kaung Myat San Oo1, Cihan Asci1 Analog Devices, Wilmington, MA, 2Ana
ISSCC 2026 Session 11 Data Converters
An 8b 20GS/s Time-Interleaved ADC with 2.6mW 1GS/s Hybrid Voltage/Time-Domain Sub-ADC in 12nm FinFET
Daisuke Miyazaki, Yuki Yagishita, Mika Takasaki, Shun Nagata, Takeru Nogamida, Yudai Abe, Kazutoshi Tomita, Kazunori Has
Satoshi Yoshizawa, Atsuya Suzuki, Soichi Kato, Takahiro Naito, Keigo Bunsen, Tomohiro Matsumoto, Yasushi Katayama Sony Semiconductor Solutions, Atsugi, Japan Abstract A 2.6mW, 1GHz, 42dB-SNDR sub-ADC is presented. A hybr
ISSCC 2026 Session 11 Data Converters
A Compact 7b 175GS/s Linearized Time-Interleaved Slope ADC with Switched Input Buffers
Ewout Martens, Angelo Parisi, Anirudh Kankuppe, Adam Cooman, Hanyue Li, Steven Van Winckel, Pratap Renukaswamy, Lucas Mo
conversion. Samplers with switched buffers are proposed to realize wideband sampling in rank 1 driven by a multi-phase clock generated by a delay line with feedforward coupling. Making the slope nonlinear compensates sta
Jorge Lagos Benites, Nereo Markulić, Jan Craninckx imec, Leuven, Belgi
ISSCC 2026 Session 11 Data Converters
A 13b 500MS/s 94dB-SFDR Resistive-Input Pipelined-SAR ADC with Linear and Efficient Current-Buffer-Based Integrating Sampler
Xiyu He, Mingyang Gu, Yunsong Tao, Siyu Huang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie
Abstract This work proposes a pipelined-SAR ADC featuring a current-buffer-based integrating sampler that presents a resistive input with good linearity. A floating charge transferrer (FCT) with multi-bit pre-conversion
Tsinghua University, Beijing, China
ISSCC 2026 Session 11 Data Converters
A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension
Michele Rocco*1, Gabriele Zanoletti*1, Alessia Ceroni*1, Giacomo Tombolan1, Gabriele Bè1,2, Luca Ricci1, Salvatore Levan
(ECAs) 1 Abstract This paper presents a 28nm CMOS 500MS/s 12b three-stage pipeline SAR ADC based on a triple-cascode single-stage floating residue amplifier with virtual supply extension to improve its efficiency and lin
Luca Bertulessi1, Carlo Samori1, Andrea Giovanni Bonfanti1 Politecnico
ISSCC 2026 Session 11 Data Converters
A 28nm CMOS SAR-Based Continuous-Time Pipeline ADC with 103dB SFDR and 270MHz Bandwidth Using NCF and DAC Error Calibration
Qilong Liu1, Robert Rutten1, Muhammed Bolatkale1, Arda Aralioglu1, Gilbert Hardeman1, Emil Siby1, Patrick van Mourik1, V
receivers achieves -95dBc THD and 103dB SFDR in 270MHz bandwidth, exceeding state-of-the-art by >20dB. Wideband high spectral purity is realized with a highly linear all-pass filter, high- SFDR coarse ADCs, a fast tone-b
NXP Semiconductors, Eindhoven, The Netherlands, 2NXP Semiconductors, D
ISSCC 2026 Session 11 Data Converters
A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration
Jingpeng Wang1, Bingrui Li1, Haoyang Luo1, Mingtao Zhan2, Xiyu He2, Dawei Shen1, Lu Jie2, Xiyuan Tang1
Abstract This paper presents a 14b 400MS/s Pipelined-SAR ADC utilizing a front-end TDC with a linearized rail-to-rail input VTC. A background calibration engine corrects VTC gain and timedomain offset errors by monitorin
Peking University, Beijing, China, 2Tsinghua University, Beijing, Chin
ISSCC 2025 Session 24 Data Converters
A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET
Junhua Shen1, Wei-Hung Chen2, Efram Burlingame3, Stephen Weinreich1,
Michael Elliott4, Stuart McCracken1, Jack Kenney2, Janet Brunsilius3, Anil Korkmaz5, Enrique Alvarez Fontecilla3, Nevena Rakuljic3, Ushma Mehta3, Ben Sullivan1, Jeremy Scuteri5, Bac Binh Luu3, Mitchell Nichols3, Dara Mar
ISSCC 2025 Session 24 Data Converters
An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with
Concurrent Residue Transfer and Quantization, and Automatic, Buffer Power Gating
Yunsong Tao, Mingtao Zhan, Mingyang Gu, Xiyu He, Yuxuan He, Zhishuai Zhang, Yi Zhong, Lu Jie, Nan Sun Tsinghua University, Beijing, China High-speed (~10GS/s) medium-resolution (~8b) ADCs are key blocks for wideband appl
ISSCC 2025 Session 24 Data Converters
A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC
Cheng-En Hsieh*1, Gabriele Manganaro*2, Sheng-Hui Liao*1, Jack Weng*1,
Tsun-Yuan Fan1, Alec Chin1, Tsung-Chih Hung1, Jonathan X Wu2, Chi-Lun Lo2, Andy Pan1, Ming-Hang Hsieh1, Yun-Shiang Shu1, Wei-Hsin Tseng1, Kuan-Dar Chen1 MediaTek, Hsinchu, Taiwan MediaTek, Woburn, MA 1 Each sub-ADC, cloc
ISSCC 2025 Session 24 Data Converters
A 72GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Inputs in 16nm FinFET
Yannan Zhang1, Minglei Zhang1, Zehang Wu1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
traffic have driven optical modules to scale beyond 100Gb/s. This evolves aggressive bandwidth and SNDR frontiers for their ADCs in the receiver to cope with advanced modulations and oversampling rates. Time-interleaving
University of Macau, Macau, China Instituto Superior Tecnico/Universit
ISSCC 2025 Session 24 Data Converters
A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input
Zijian Liu1, Minglei Zhang1, Wei Zhang1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
unpredictable and non-Gaussian error behaviors in the A/D conversion, which cannot be tolerated by applications such as lowbit-error-rate serial link receivers, radar, and instrumentation [1-5]. Time-domain (TD) ADCs [6-
University of Macau, Macau, China Instituto Superior Tecnico/Universit
ISSCC 2025 Session 24 Data Converters
A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz ERBW
Junlin Zhong1, Minglei Zhang1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 The demand for medium-resolution GS/s ADCs is increasing in DSP-based wireline communication. Enhancing energy and area efficiency of the unit ADC is cr
University of Macau, Macau, China
ISSCC 2025 Session 24 Data Converters
A 14b 1GS/s Single-Channel Pipelined ADC with a Parallel-Operation SAR Sub-Quantizer and a DynamicDeadzone Ring Amplifier
Yue Cao1, Yi Shen1,2, Shubin Liu1,2, Haolin Han1, Hongzhi Liang1, Li Dang1,
and high resolution (&14b) are required for wireless communication and instrumentation applications. The conventional pipelined architecture is usually power-hungry due to the substantial use of residue amplifiers (RAs)
Dengquan Li1, Ruixue Ding1,2, Zhangming Zhu1,2 Xidian University, Xi’a
ISSCC 2025 Session 24 Data Converters
A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration
Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun
The pipelined ADC is an attractive choice for high-speed and high-resolution applications. Its most important building block is the residue amplifier. Compared with conventional closed-loop amplifiers, open-loop amplifie
Tsinghua University, Beijing, China
ISSCC 2025 Session 18 Data Converters
A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR
Bram Veraverbeke, Filip Tavernier
Cryo-CMOS has shown great potential to implement fast, scalable and efficient readout circuits for quantum bits (qubits). Several cryo-CMOS circuits for the dispersive readout of transmon qubits [1-2] or the reflectometr
KU Leuven ESAT-MICAS, Leuven, Belgium
ISSCC 2025 Session 18 Data Converters
A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMS with Progressive Conversion and Floating-Charge-Transfer Amplifier
Siyu Huang, Zhishuai Zhang, Xiyu He, Mingyang Gu, Yunsong Tao, Yi Zhong,
before the ADC often occupies a significant area and noise contribution, especially when a Nyquist-sampling ADC is used and a sharp anti-aliasing BBF is thereby necessary (Fig. 18.7.1a). The continuous-time ∆Σ modulator
Nan Sun, Lu Jie Tsinghua University, Beijing, China In the analog fron
ISSCC 2025 Session 18 Data Converters
An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration
Zhuoyi Chen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan,
realized utilizing the energy-efficient pipelined-SAR architecture [1-2]. However, a large sampling capacitance is required to suppress the thermal noise, making ADCs challenging to drive. Although the integrated driving
Ru Huang, Linxiao Shen Peking University, Beijing, China High-resoluti
ISSCC 2025 Session 18 Data Converters
A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting
Siyuan Ye, Jiajia Cui, Jihang Gao, Jie Li, Xing Zhang, Ru Huang, Linxiao Shen
With the development of high-resolution ADCs (>13b) leveraging the SAR topology, the pursuit of power efficiency in ADC design continues to make remarkable strides [1-5]. However, as the capacitance of the capacitive DAC
Peking University, Beijing, China
ISSCC 2025 Session 18 Data Converters
A 184.8dB-FoMS 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique
Zongnan Wang, Bingrui Li, Jiajun Tang, Zhongyi Wu, Haoyang Luo, Yuan Wang, Xiyuan Tang
high-resolution ∆Σ modulator, is favored for sensor nodes demanding high accuracy, good energy efficiency, and easy system integration. Conventional zoom ADCs, constrained by the low quantization levels of ∆Σ modulators,
Peking University, Beijing, China The incremental zoom ADC, integratin
ISSCC 2025 Session 18 Data Converters
A 12.2µW 99.6dB-SNDR 184.8dB-FOMS DT Zoom PPD ∆ΣM with Gain-Embedded Bootstrapped Sampler
Yaohui Luan, Xinhang Xu, Jihang Gao, Jiajia Cui, Zhuoyi Chen, Siyuan Ye,
consumption as they determine the overall noise and linearity performance. To achieve high resolution, discrete-time (DT) ∆ΣMs require large sampling capacitors [1-3]. This induces a huge driving burden for the ADC input
Ru Huang, Linxiao Shen Peking University, Beijing, China Input stages
ISSCC 2025 Session 18 Data Converters
A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMS in 1kHz BW *Equally Credited Authors (ECAs) An issue of 3-level switching is that it suffers from nonlinearity caused by VCM error. As shown in Fig. 18.1.3, without VCM error, the asymmetric capacitor mismatch in a differential 3-level DAC only causes an offset (common-mode mismatch). But with VCM error, the characteristic curve of DAC becomes nonlinear. This nonlinearity mainly introduces the 2nd-order harmonic distortion, as the VCM usage is a bilaterally symmetry pattern versus DAC input value. This nonlinearity can be neatly solved by the system-level chopping. When the polarity of chopping signal is reversed, the DAC mismatch is also reversed. In this manner, the differential DAC mismatch is averaged out, as well as the offset caused by asymmetric DAC mismatch. In this design, the VCM voltage is generated by two 2.5MΩ off-chip resistors. High-resolution ADCs with micro power and kHz-level BW have wide applications in portable instrumentation, implantable devices and smart sensors. To enhance flexibility and improve energy efficiency, many systems require duty-cycled operation and expect power scaling
with speed. State-of-the-art high-resolution ADC solutions include DSMs, zoom, SAR and, noise-shaping (NS) SAR ADCs. The
THD of -116dB, and it consumes high power due to the 4th-order loop filter. The zoom ADC in [2] combining with a coarse SAR and a fine DSM achieves 119.8dB SNR, but it can only process DC signals. The dynamic zoom ADCs [
ISSCC 2024 Session 9 Data Converters
A 2.72fJ/conv 13b 2MS/s SAR ADC Using Dynamic Capacitive Comparator with Wide Input Common Mode
Sewon Lee, Hyein Kang, Minjae Lee
As SAR resolution increases, comparator power increases exponentially [1-2]. This problem should be mitigated, especially in battery-powered applications. Recent low power and noise comparators utilized dynamic pre-ampli
Gwangju Institute of Science and Technology, Gwangju, Korea
ISSCC 2024 Session 9 Data Converters
A 9.3nV/rtHz 20b 40MS/s 94.2dB DR Signal-Chain Friendly Precision SAR Converter
Rares Bodnar1,2, Henry Kennedy1, Christopher P Hurrell1, Asif Ahmad1,
Mark Vickery1, Luke Smithers1, William Buckley3, Monsoon Dutt1, Pasquale Delizia4, Derek Hummerston1, Pawel Czapor3 return high, marking the acquisition of the complementary set of 8 sampling DACs. The remaining timing m
ISSCC 2024 Session 9 Data Converters
A 94.3dB SNDR 184dB FoMs 4th-Order Noise-Shaping SAR ADC with Dynamic-Amplifier-Assisted Cascaded Integrator
Kai-Cheng Cheng1, Soon-Jyh Chang1, Chung-Chieh Chen2, Shuo-Hong Hung2
Upbeat Technology, Taipei, Taiwan 1 2 The noise-shaping (NS) SAR ADC, which features the advantages of sigma-delta ADCs and SAR ADCs, is high accuracy and low power, so it stands out as a great choice for audio applicati
National Cheng Kung University, Tainan, Taiwan
ISSCC 2024 Session 9 Data Converters
A 6th-Order Quadrature CTDSM using Double-OTA and Quadrature NSSAR with 171.3dB FoMs in 14nm We introduce an extra CC path (shaded blocks in Fig. 9.6.3) to the integrator within NSSAR to achieve even higher SNR. This transforms the NTF of the NSSAR to the desired band, resulting in further suppressed quantization noise in the target bandwidth. Figure 9.6.3 shows the effectiveness of our QNSSAR with the simulated quantization noise using three different quantizers in a quadrature CT-DSM with ideal models. The resulting SQNR utilizing QNSSAR is 93.52dB while the conventional SAR, and NSSAR give 76.35dB, and 88.36dB, respectively.
Jongmi Lee, Seong-Eun Cho, Jaehoon Lee, Yong Lim, Seunghyun Oh,
low-intermediatefrequency (low-IF) architecture is widely chosen for energy efficient wireless communication systems, such as Bluetooth Low Energy (BLE) and IoT. The low-IF architecture typically requires filters for anti-
Jongwoo Lee, Sung-Ung Kwak Samsung Electronics, Hwasung, Korea In orde
ISSCC 2024 Session 9 Data Converters
A 118.5dBA DR 3.3mW Audio ADC with a Class-B Resistor
DAC, Non-Overlap DEM and Continuous-Time Quantizer
increased the need for lowpower, high dynamic range (DR) audio ADCs. In these applications, the DR specification determines the maximum distance at which a low-cost microphone can obtain a good quality recording. THD+N (S
Anand Subramanian, Tanmay Halder, Laxmi Vivek Tripurari, Anand Kannan
ISSCC 2024 Session 9 Data Converters
A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique
Zhuoyi Chen1, Linxiao Shen1, Siyuan Ye1, Jihang Gao1, Jie Li1, Jiajia Cui1,
Information Technology of Peking University, Hangzhou, China 1 2 The residue amplifier (RA) in a pipelined-SAR ADC eases the noise requirement of the back-end stage, making the architecture energy-efficient. However, to ac
Xinhang Xu1, Yaohui Luan1, Hao Zhang2, Le Ye1,3, Ru Huang1 Peking Univ
ISSCC 2024 Session 9 Data Converters
A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs
Xiyu He, Mingyang Gu, Hanjun Jiang, Yi Zhong, Nan Sun, Lu Jie
Wideband (BW >100MHz) and high-dynamic-range (DR >70dB) ADCs are in high demand for next-generation wireless standards. Conventional ADC solutions face challenges in both performance and efficiency: CTDSMs demonstrate fav
Tsinghua University, Beijing, China
ISSCC 2024 Session 9 Data Converters
A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm
Yong Lim*, Jaehoon Lee*, Jongmi Lee, Kwangmin Lim, Seunghyun Oh,
energy-efficient alternatives to OTAs for switchedcapacitor residue amplifiers. A ring amplifier is essentially a cascaded multi-stage inverter-based amplifier that is stabilized by a dominant pole at the last stage output w
Jongwoo Lee, Sung-Ung Kwak Samsung Electronics, Hwaseong, Korea *Equal
ISSCC 2024 Session 9 Data Converters
A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting
Siyuan Ye1, Linxiao Shen1, Jihang Gao1, Jie Li1, Zhuoyi Chen1, Xinhang Xu1,
Information Technology of Peking University, Hangzhou, China 1 2 The pipelined-SAR ADC has become popular in wide-bandwidth and high-resolution applications due to its power-efficient architecture [1]. In the pursuit of h
Jiajia Cui1, Hao Zhang2, Xing Zhang1, Le Ye1,3, Ru Huang1 Peking Unive
ISSCC 2023 Session 17 Data Converters
A Single-Channel 10GS/s 8b >36.4dB SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS
Qian Chen1, Yuan Liang*1, Chirn Chye Boon1, Qing Liu2
Kun Gao Xinxin Technologies, Singapore, Singapore *Equally Credited Authors (ECAs) 1 2 High data throughput and wideband network communications demand high-speed (several to tens of GS/s), moderate-resolution (6-10b) ADC
Nanyang Technological University, Singapore, Singapore
ISSCC 2023 Session 17 Data Converters
A 3mW 2.7GS/s 8b Subranging ADC with Multiple-ReferenceEmbedded Comparators
Jia-Ching Wang, Tai-Haur Kuo
A subranging ADC is a good choice for wideband applications since the numerous comparators for a flash ADC can be avoided [1-5]. However, despite the reduced number of comparators that a subranging ADC requires, these co
National Cheng Kung University, Tainan, Taiwan
ISSCC 2023 Session 17 Data Converters
A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew Calibration
Yi-Hu Wang, Soon-Jyh Chang
With the development of broadband wireless communication and DSP-based wireline communication, there is a rising demand for medium-resolution (6~8bit) ADCs with multi-gigahertz sampling rates and low power consumption. T
National Cheng Kung University, Tainan, Taiwan
ISSCC 2023 Session 17 Data Converters
A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor
Mingtao Zhan, Lu Jie, Nan Sun
Next-generation wireless standards (e.g., WiFi-7) advancing towards wider bandwidth and higher order modulation require ADCs with GHz sampling rates and over 12b resolution. Although conventional pipelined ADCs can satis
Tsinghua University, Beijing, China
ISSCC 2023 Session 17 Data Converters
A 750mW 24GS/s 12b Time-Interleaved ADC for Direct RF Sampling in Modern Wireless Systems
Sandeep Santhosh Kumar1, Masahiro Kudo1, Vlad Cretu1, Antoine Morineau1,
Atsushi Matsuda2, Minori Yoshida2, Masazumi Marutani2, Aadil Hussain Maniyar1, Jay Kumar1 Socionext Europe, Maidenhead, United Kingdom Socionext, Yokohama, Japan 1 2 An ADC with a sampling rate of tens of GS/s and a high
ISSCC 2023 Session 17 Data Converters
A 14b 16GS/s Time-Interleaving Direct-RF Synthesis DAC with T-DEM Achieving -70dBc IM3 up to 7.8GHz in 7nm
Wei-Hsin Tseng*1, Willy Lin*1, Chung-Wei Hsu1, Chang-Yang Huang1,
Yu-Sian Lin1, Hung-Yi Huang1, HsinWei Chen1, Sheng-Hui Liao1, Kuan-Dar Chen1, Jon Strange2, Gabriele Manganaro3 MediaTek, HsinChu, Taiwan, 2MediaTek, Kent, United Kingdom, 3MediaTek, Woburn, MA *Equally Credited Authors
ISSCC 2023 Session 17 Data Converters
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with 2× Interpolating Sense-Amplifier-Latches
Abdullah Serdar Yonar1,2, Pier Andrea Francese1, Matthias Brändli1,
2 Circuit innovations in medium-low resolution ADCs are among the key enablers to achieving higher data rates, currently at 224Gb/s [1], in the next-generation datacommunication links based on sophisticated DSP technique
Marcel Kossel1, Mridula Prathapan1, Thomas Morf1, Andrea Ruffino1, Tae
ISSCC 2023 Session 17 Data Converters
A 2×-Interleaved 9b 2.8GS/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input
Hongzhi Zhao1, Minglei Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 By increasing the number of bits in each conversion cycle, the sampling rate of SAR ADCs can be considerably extended while maintaining superior energ
University of Macau, Macao, China
ISSCC 2023 Session 10 Data Converters
A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping
Yanbo Zhang*1,2, Junyan Hao1,2, Shubin Liu2, Zhangming Zhu2, Yan Zhu1,
Chi-hang Chan*1, R. P. Martins1,3 University of Macau, Macau, China Xidian University, Xi’an, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal *Equally Credited Authors (ECAs) 1 2 Emerging wirele
ISSCC 2023 Session 10 Data Converters
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer
Zongnan Wang1, Lu Jie2, Zichen Kong1, Mingtao Zhan2, Yi Zhong2, Yuan Wang1, Xiyuan Tang1
good energy efficiency. Lately, the incremental ADC is drawing rising attention by favoring system integration with its easy multiplexing and simple digital filtering. By combining a low-power SAR with a low-distortion ∆
Peking University, Beijing, China, 2Tsinghua University, Beijing, Chin
ISSCC 2023 Session 10 Data Converters
A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-PredictionUnrolled Scheme
Hongshuai Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Shaping the interstage gain error in two-step oversampling ADCs has demonstrated a decent error suppression with a variety of mechanisms. The intersta
University of Macau, Macau, China
ISSCC 2023 Session 10 Data Converters
A Rail-to-Rail 12MS/s 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting
Manxin Li1, Calvin Yoji Lee1, Ahmed ElShater1, Yuichi Miyahara2, Kazuki Sobue2,
utilizing the power-efficient SAR topology at medium speed (1-20MSps) [1-4]. However, highresolution discrete-time Nyquist ADCs are difficult to drive, especially at high sampling frequencies, due to their large input sa
Koji Tomioka2, Un-Ku Moon1 Oregon State University, Corvallis, OR Asah
ISSCC 2023 Session 10 Data Converters
A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer
Yuefeng Cao1, Minglei Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 High-speed pipelined ADCs rely on fast and accurate residue amplification which often necessitates calibration, thus suffering from potential converge
University of Macau, Macau, China
ISSCC 2023 Session 10 Data Converters
A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness
Junyan Hao1,2, Minglei Zhang1, Yanbo Zhang1,2, Shubin Liu2, Zhangming Zhu2,
Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,3 University of Macau, Macau, China Xidian University, Xi’an, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 A highly integrated wireline receiver w