A 72GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Inputs in 16nm FinFET

📋 论文概要

该论文提出了一款72GS/s 9位时间交织流水线逐次逼近（Pipeline-SAR）模数转换器（ADC），采用16nm FinFET工艺实现。针对时间交织中带宽失配和隐式失真导致的SFDR和ENOB退化问题，通过校准技术实现了在20GHz和奈奎斯特输入下分别达到55.3dB和49.3dB的SFDR。

💡 主要创新点

• 提出了一种适用于近100GS/s高速ADC的时间交织Pipeline-SAR架构，有效缓解了高交织因子带来的性能限制。
• 开发了针对带宽失配和隐式失真的校准技术，显著提升了宽带输入下的SFDR和线性度。

🏷 关键词

📄 原文摘要

traffic have driven optical modules to scale beyond 100Gb/s. This evolves aggressive bandwidth and SNDR frontiers for their ADCs in the receiver to cope with advanced modulations and oversampling rates. Time-interleaving (TI) is indispensable for such the near-hundred GS/s envelope, but a massive TI factor confines the achievable SFDR as well as ENOB at wideband inputs over 20GHz [1]. The constraint primarily stems from two regimes, which are the bandwidth mismatch and implicit distortion in the interleaver. Relying solely on timing skew calibration [1-3] for skew-associated impairments is not sufficient since it only provides first-order correction for bandwidth mismatch. An additional order of amendment can be achieved by tuning the sampling capacitors [1], but the error detection mechanism remains unsound. Furthermore,

👥 作者与机构

Yannan Zhang1, Minglei Zhang1, Zehang Wu1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1

University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 The ever-increasing demands of communication