2025

AI Era Innovation Matrix Navid Shahriari

From Chips to Thoughts: Building Physical Intelligence into Robotic Systems Daniela Rus

AI Revolution Driven by Memory Technology Innovation Jaihyuk Song

The Crucial Role of Semiconductors in the Software-Defined Vehicle Peter Schiefer

A 77GHz Hybrid TDMA-MIMO Phased-Array Radar with 186m Detection Range and 3cm Range Resolution

A 132-to-148GHz CMOS 4TX-4RX FMCW Radar Transceiver Array with Cavity-Backed Antenna-in-Package Achieving 28dBm EIRP

A D-Band 2D-Scalable 4×4 Active Reflective Relay with Orthogonally Polarized On-Chip TX/RX Antennas and In-Front-End Common-Centroid Fast Azimuth/Elevation Angle-of-Arrival Detection

A 2-TRX IR-UWB Transceiver with Shared Antennas Supporting Channels 5 to 12 in Compliance with IEEE 802.15.4/4z Standards

A 28nm Multimode Multiband RF Transceiver with Harmonic-Rejection TX and Spur-Avoidance RX Supporting LTE Cat1bis

A 256-Element Ka-Band CMOS Phased-Array Receiver Using Switch-Type Quadrature-Hybrid-First Architecture for Small Satellite Constellations element quadrature hybrid when the switches are turned off in quadrature-hybrid mode. On the other hand, in through mode, the midpoint of the two inductors can be connected to the grounds by turning the switches on. As a result, signals input to the IN H and IN V ports will flow to the OUT L/H and OUT R/V ports respectively after a 45-degree phase shift.

A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS

A Compact Full-Duplex Receiver with Wideband Multi-Domain Hilbert-Transform-Equalization Cancellation Based on Multi-Stage APFs Achieving 65dB SIC Across 120MHz BW

A Gm-C RF Quadrature-Current-Generation Technique with 40dB IRR in 0.65V 2mW Multi-Mode CMOS GNSS Receiver

A 200MHz-BW Blocker-Tolerant Receiver with Fifth-Order Filtering Achieving 19dBm Adjacent-Channel IIP3

Circuits that Solve Optimization Problems by Exploiting Physics Inequalities

p-Circuits: Neither Digital nor Analog

Reversing Scattering to Perform Deep-Tissue Optical Imaging and the Current Need for a Suitable Optoelectronic Solution Changhuei Yang

Skin-Inspired Electronics: An Emerging Sensing and Computing Platform

A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction

An 8.62μW 75dB-DRSoC End-to-End Spoken-LanguageUnderstanding SoC with Channel-Level AGC and Temporal-Sparsity-Aware Streaming-Mode RNN

A Cryo-BiCMOS Controller for 9Be+-Trapped-Ion-Based Quantum Computers

Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with 4.6μV Precision and 4.1nV/Hz0.5 Noise Co-Integrated with the Single Electron Transistor at 60mK

An 18.5μW/qubit Cryo-CMOS Charge-Readout IC Demonstrating QAM Multiplexing for Spin Qubits

A Via-Programmable DNN-Processor Fabrication Toward 1/40th Mask Cost

A 22nm 104.5TOPS/W µ-NMC-∆-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks

A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices loss of accuracy. In HV mode, the M2-IPU aligns INM based on both ∆PDE and ∆PDSS, with extra shifting in INM from ∆PDSS, which increases INM sparsity, further enhancing EEF. In phase 2 (Ph2), the OUT-PRO processes the activation function of the M2-CIM outputs and

A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two’s-Complement MAC for CNNs and Transformers

A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <2-30 Loss for Compound AI

A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference connection using the 3rd-metal layer and connect the corresponding diagonal in the 4th layer; the row connection is in the 5th layer. This method circumvents the need for numerous MAC circuits and read ports as is the case for previous T-CIM works [7,8], resulting in a reduction in area and power consumption.

A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer

A 3.9mW 200words/min Neural Signal Processor in Speech Decoding for Brain-Machine Interface

A 1024-Channel 0.00029mm2/ch 74nW/ch Online Spatial Spike-Sorting Chip with Event-Driven Spike Detection and Self-Organizing Map Clustering

A 65nm Uncertainty-Quantifiable Ventricular Arrhythmia Detection Engine with 1.75µJ per Inference

A Neuroprosthetic SoC with Sensory Feedback Featuring Frequency-Splitting-Based Wireless Power Transfer with 200Mb/s 0.67pJ/b Backscatter Data Uplink and Unsupervised Multi-Class Spike Sorting

Event-Based Spatially Zooming Neural Interface IC with 10nW/Input Reconfigurable-Inverter Fabric and Input-Adaptive Quantization

A 3.47 NEF 175.2dB FOMS Direct Digitization Front-End Featuring Delta Amplification for Enhanced Dynamic Range and Energy Efficiency in Bio-Signal Acquisition

A 4.6µW 3.3-NEF Biopotential Amplifier with 133VPP Common-Mode Interference Tolerance and 102dB Total Common-Mode Rejection Ratio for Two-Electrode Recording System

Tomahawk5: 51.2Tb/s 5nm Monolithic Switch Chip for AI/ML Networking

RNGD: A 5nm Tensor-Contraction Processor for Power-Efficient Inference on Large Language Models

An On-Device Generative AI Focused Neural Processing Unit in 4nm Flagship Mobile SoC with Fan-Out Wafer-Level Package

SambaNova SN40L: A 5nm 2.5D Dataflow Accelerator with Three Memory Tiers for Trillion Parameter AI

Sensor-Less Laser Voltage-Probing Attack Detection via Run-Time-Leakage-Shift Monitoring with 4.35% Area Overhead

A 28nm 4.05µJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing

A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-Party Computation

An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies and implemented in the 3nm (GAA) and 8nm (FinFet) technology nodes. The evaluations were performed on the test dies of both technologies across various process corners and operational conditions, where each die contains six PUF macros.

An Eye-Opening Arbiter PUF for Fingerprint Generation Using Auto-Error Detection for PVT-Robust Masking and Bit Stabilization Achieving a BER of 2e-8 in 28nm CMOS

A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process

A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMS in 1kHz BW *Equally Credited Authors (ECAs) An issue of 3-level switching is that it suffers from nonlinearity caused by VCM error. As shown in Fig. 18.1.3, without VCM error, the asymmetric capacitor mismatch in a differential 3-level DAC only causes an offset (common-mode mismatch). But with VCM error, the characteristic curve of DAC becomes nonlinear. This nonlinearity mainly introduces the 2nd-order harmonic distortion, as the VCM usage is a bilaterally symmetry pattern versus DAC input value. This nonlinearity can be neatly solved by the system-level chopping. When the polarity of chopping signal is reversed, the DAC mismatch is also reversed. In this manner, the differential DAC mismatch is averaged out, as well as the offset caused by asymmetric DAC mismatch. In this design, the VCM voltage is generated by two 2.5MΩ off-chip resistors. High-resolution ADCs with micro power and kHz-level BW have wide applications in portable instrumentation, implantable devices and smart sensors. To enhance flexibility and improve energy efficiency, many systems require duty-cycled operation and expect power scaling

A 12.2µW 99.6dB-SNDR 184.8dB-FOMS DT Zoom PPD ∆ΣM with Gain-Embedded Bootstrapped Sampler

A 184.8dB-FoMS 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique