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ISSCC 2025Session 22 · MEMORY INTERFACEMemory

An 850μW 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文提出了一款用于HBM4的注入锁定正交时钟生成器,功耗仅850μW,频率范围2-5GHz,具备抖动滤波和即时切换功能,解决了低功耗时钟生成中的抖动抑制和快速响应问题。

💡 主要创新点

核心指标
850μW功耗,2-5GHz频率范围
重要性
发表年份
ISSCC 2025

🏷 关键词

注入锁定正交时钟生成抖动滤波低功耗HBM4

📄 原文摘要

KAIST, Daejeon, Korea 1 2 *Equally Credited Authors (ECAs) The explosive expansion of generative AI, in various industries, has led to a surge in demand for high-bandwidth memory (HBM) devices that feature thousands of DQ pins to maximize data bandwidth (BW) [1-3]. The next-generation HBM4 is expected to achieve over 2TB/s using 64 DWORDs, each with 32 DQ pins in six DQ groups (GRs). Like other DRAM devices, HBM operates internally at a quarter rate to ensure timing margins: utilizing quadrature clocks SIN,X, where X = {I, Q, IB, QB}, each operating at fQCK = 2.5GHz (with a period of TQCK = 400ps), which are generated from the differential WDQS within each DWORD. Top left of Fig. 22.2.1 shows a typical clock-distribution network (CDN) in HBM interfaces [4]. In this scheme, all four SIN,X are transmitted separately to DQ GRs through parallel routings and repeaters, presenting challenges that are particularly critical for HBM. The parallel

👥 作者与机构

Jeongbeom Seo*1, Yoonseo Cho*1,2, Yuhwan Shin1,2, Jaehyouk Choi1

Seoul National University, Seoul, Korea

分类:Memory · 年份:ISSCC 2025