← 返回论文列表 📄 下载原文 PDF  ISSCC 2025 · 8.8
ISSCC 2025Session 8 · DIGITAL TECHNIQUES FOR SYSTEM ADAPTATION, POWER MANAGEMENT AND CLOCKINGDigital Circuits16nm CMOS

Fine-Grained Spatial and Temporal Thermal Profiling of a 16nm CMOS Buck Converter and SoC Load-Current Emulator Using Low-Voltage Micron-Scale Thermal Sensors

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文提出了一种细粒度时空热分布测量技术,用于16nm CMOS降压转换器和SoC负载电流仿真器,解决了高功率密度单片和异构3D SoC中局部热点对性能和可靠性的瓶颈问题。通过集成温度传感器阵列和负载电流仿真器,实现了对芯片热分布的精确监测和仿真。

💡 主要创新点

工艺节点
16nm CMOS
重要性
发表年份
ISSCC 2025

🏷 关键词

热分布测量降压转换器SoC负载仿真局部热点16nm CMOS

📄 原文摘要

Krishnan Ravichandran, James W. Tschanz, Vivek De Intel, Hillsboro, OR Localized hotspots across high-power-density monolithic systems-on-chip (SoCs) and heterogenous 3D SoCs with integrated voltage regulators (IVR) pose major bottlenecks to performance and reliability, especially as demand for compute density across a wide range of applications continues to grow unabated [1-2]. Floating point units and matrix/vector multipliers for AI/ML and other special-purpose accelerators, designed to deliver extreme performance on demand for a variety of workloads, generate localized thermal hotspot profiles at fine granularity that vary across time and workloads [3-4]. This is further aggravated in 3D integration since heat dissipation occurs vertically through the thinner dies to improved thermal interface materials, resulting in larger localized temperature gradients (>10°C) across a few 100µm [5]. Therefore, fine-grained thermal profiling as well

👥 作者与机构

Zakir Ahmed, Suhwan Kim, Charles Augustine, Harish K. Krishnamurthy,

分类:Digital Circuits · 年份:ISSCC 2025