Digital Circuits

SharpSAT: A Heuristic-Learning-Based SAT Accelerator Achieving 0.8μs/16.1μs Solution Time in SAT/UNSAT Cases

COBI: A Degree-of-56 Column-Bipartite Densely Connected Digital Ising Chip with 8b Spin Coefficients

A 28nm Mode-Reconfigurable CAM-CIM Hybrid Complete 3-SAT Solver Supporting Conflict-Driven Clause Learning with 100% Solvability

A Hybrid-Bonded 12.1TOPS/mm2 56-Core DNN Processor with 2.5Tb/s/mm2 3D Network on Chip

Proactive Power Management-Based Supply Regulation with Online Learning for Variation-Tolerant Workload-Aware Droop Mitigation in 28nm CMOS

A 0.008mm2 16-to-1600MHz All-Digital Fractional Divider Using AUX-DLL for Background LMS-Based DTC Calibration

A 2nm Clock-Edge Architecture for Processor Clock-Power Reduction

A Dynamic Performance Augmentation in a 3nm-Plus Mobile CPU

A 3nm, 400TOPS, 1080k DMIPS SoC with Chiplet Support for ASIL D Automotive Cross-Domain Applications

An On-Cell Monitoring and Balancing System With Near-Field Communications for EV Batteries

Fine-Grained Spatial and Temporal Thermal Profiling of a 16nm CMOS Buck Converter and SoC Load-Current Emulator Using Low-Voltage Micron-Scale Thermal Sensors

A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS

A 0.024mm2 All-Digital Fractional Output Divider with 257fs Worst-Case Jitter Using Split-DTC-Based Background Calibration

A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150µA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time

A Dynamically Reconfigurable Digital-Integrated Voltage-Regulator Fabric for Energy-Efficient DVFS in Multi-Domain SoCs

Dynamic Guard-Band Features of the IBM zNext System

A 13.5µW 35-Keyword End-to-End Keyword Spotting System Featuring Personalized On-Chip Training in 28nm CMOS

A 28nm 18.1µJ/Acquisition End-to-End GPS Acquisition Accelerator with Energy-Accuracy-Driven Mixed-Radix IFFT and ROM-Assisted Computing

SKADI: A 28nm Complete K-SAT Solver Featuring Dual-Path SRAM-Based Macro and Incremental Update with 100% Solvability

SHINSAI: A 586mm2 Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory

A 2-Dimensional mm-Scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6×2.15mm2 SoC and bySPI Chiplets

IBM Telum II Processor Design-Technology Co-Optimizations

A 47.3-to-58.4GHz Differential Quasi-Class-E Colpitts Oscillator Achieving 198.8dBc/Hz FoMT

An 18.5-to-23.6GHz Quad-Core Class-F23 Oscillator Without 2nd/3rd Harmonic Tuning Achieving 193dBc/Hz Peak FoM and 140-to-250kHz 1/f3 PN Corner in 65nm CMOS

A 9.05-to-37.0GHz LO Generator with Magnetic Mode Switching and Tuning-Free Octave-Bandwidth Common-Mode Resonator Achieving >190.7dBc/Hz FoM

A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning

A 380µW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with sub-20µs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS

A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing

A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization selectors arranged in two stages, reducing the critical path by 85% compared to the design with a 1024b selector. An additional LFSR is included to ensure that the resulting distribution reaches uniformity.

VIP-Sat: A Boolean Satisfiability Solver Featuring 5×12 Variable In-Memory Processing Elements with 98% Solvability for 50-Variables 218-Clauses 3-SAT Problems

A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance

A Monolithic 10.5W/mm2 600MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS

KASP: A 96.8% 10-Keyword Accuracy and 1.68µJ/Classification Keyword Spotting and Speaker Verification Processor Using Adaptive Beamforming and Progressive Wake-Up

A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS the delay of the DTC based on the LMS calibration method. To satisfy timing constraints, the critical digital blocks are designed with customized logic circuits using low-threshold transistors. The whole HPLL can operate at the minimum voltage of 0.45V (D/VCO at 0.4V) without requiring any voltage booster or bias current.

A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET

A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator

A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU

A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion

Proactive Voltage Droop Mitigation Using Dual-ProportionalDerivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS

A/mm2 Scalable Distributed All-Digital 6×6 Dot-LDOs Featuring Freely Linkable Current-Sharing Network: A Fine-Grained On-Chip Power Delivery Solution in 28nm CMOS

A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC

An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices

A Sub-0.8pJ/b 16.3Gbps/mm2 Universal Soft-Detection Decoder Using ORBGRAND in 40nm CMOS

CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition

A 1.5µW End-to-End Keyword Spotting SoC with Content-Adaptive Frame Sub-Sampling and Fast-Settling Analog Frontend

A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking

An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees

A Digital Low-Dropout (LDO) Linear Regulator with Adaptive Transfer Function Featuring 125A/mm2 Power Density and Autonomous Bypass Mode

A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration

A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur