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ISSCC 2023Session 29 · DIGITAL ACCELERATORS AND CIRCUIT TECHNIQUESDigital Circuits

A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文提出了一种异构RRAM存内计算和SRAM近存计算的SoC,用于混合帧相机和事件相机的目标跟踪任务,解决了传统帧相机CNN处理高精度但低吞吐量的问题。该SoC实现了73.53TOPS/W的能效和14.74TOPS的吞吐量。

💡 主要创新点

核心指标
73.53TOPS/W 14.74TOPS
重要性
发表年份
ISSCC 2023

🏷 关键词

目标跟踪存内计算RRAM

📄 原文摘要

Shota Konno1, Zishen Wan1, Ashwin Bhat1, Win-San Khwa2, Yu-Der Chih3, Meng-Fan Chang2, Arijit Raychowdhury1 Georgia Institute of Technology, Atlanta, GA TSMC Corporate Research, Hsinchu, Taiwan 3 TSMC Design Technology, Hsinchu, Taiwan *Equally Credited Authors (ECA) 1 2 Vision-based high-speed target-identification and tracking is a critical application in unmanned aerial vehicles (UAV) with wide military and commercial usage. Traditional frame cameras processed through convolutional neural networks (CNN) exhibit high target-identification accuracy but with low throughput (hence low tracking speed) and high power. On the other hand, event cameras or dynamic vision sensors (DVS) generate a stream of binary asynchronous events corresponding to the changing intensity of the pixels capturing high-speed temporal information, characteristic of high-speed tracking. Such event streams with high spatial sparsity processed with bio-mimetic spiking neural

👥 作者与机构

Muya Chang*1, Ashwin Sanjay Lele*1, Samuel D. Spetalnick1, Brian Crafton1,

分类:Digital Circuits · 年份:ISSCC 2023