ISSCC 2023

2023

200 篇论文 · AI / ML (28) · Power Management (24) · RF & Wireless (20) · Data Converters (15)

ISSCC 2023 Session 1 Plenary
Innovation For the Next Decade of Compute Efficiency
Lisa Su1, Sam Naffziger2
AMD, Fort Collins, CO2 1.1 Introduction With high-performance computing becoming an increasingly essential part of modern life, efficiently delivering improvements in compute performance is the defining challenge for our
AMD, Austin, TX1
ISSCC 2023 Session 1 Plenary
Shape the World with Mixed-Signal Integrated
Circuits - Past, Present, and Future, Akira Matsuzawa
Introduction The last 50 years has been an era where analog equipment has been replaced by digital devices. LP records have been replaced by Compact Discs, NTSC and PAL TV systems have been replaced by digital TVs, VHS v
Professor Emeritus of Tokyo Institute of Technology and CEO of Tech Id
ISSCC 2023 Session 1 Plenary
EU Chips Act Drives Pan-European Full-Stack Innovation Partnerships Jo De Boeck
imec and KU Leuven, Leuven, Belgium, Jean-René Lèquepeys
Germany 1. The Impact of Semiconductors and the European Chips Act In every aspect of our life and society, semiconductors play a major role and that impact is set to increase even further. The pandemic in conjunction wi
CEA-Leti and Université Grenoble Alpes, Grenoble, France Christoph Kut
ISSCC 2023 Session 1 Plenary
5G Drives Exponential Increase in Processing Needs Across all Industries Erik Ekudden
Senior Vice President & Chief Technology Officer, Ericsson, Kista, Sweden, 1. Introduction
The extreme development of semiconductor-based compute technologies has not escaped anyone but the fact that mobile communications has followed a similar trajectory may be less obvious to most. Over five generations of m
ISSCC 2023 Session 10 Data Converters
A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations
Sung-En Hsieh, Tzu-Chien Wu, Chun-Chih Hou
Direct RF sampling reduces complexity for receiver design. However, SNDR and speed specifications of its ADCs are stringent, which makes the time-interleaved (TI) ADC attractive for the required sampling rate. There is a
MediaTek, Hsinchu, Taiwan
ISSCC 2023 Session 10 Data Converters
A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness
Junyan Hao1,2, Minglei Zhang1, Yanbo Zhang1,2, Shubin Liu2, Zhangming Zhu2,
Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,3 University of Macau, Macau, China Xidian University, Xi’an, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 A highly integrated wireline receiver w
ISSCC 2023 Session 10 Data Converters
A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer
Yuefeng Cao1, Minglei Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 High-speed pipelined ADCs rely on fast and accurate residue amplification which often necessitates calibration, thus suffering from potential converge
University of Macau, Macau, China
ISSCC 2023 Session 10 Data Converters
A Rail-to-Rail 12MS/s 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting
Manxin Li1, Calvin Yoji Lee1, Ahmed ElShater1, Yuichi Miyahara2, Kazuki Sobue2,
utilizing the power-efficient SAR topology at medium speed (1-20MSps) [1-4]. However, highresolution discrete-time Nyquist ADCs are difficult to drive, especially at high sampling frequencies, due to their large input sa
Koji Tomioka2, Un-Ku Moon1 Oregon State University, Corvallis, OR Asah
ISSCC 2023 Session 10 Data Converters
A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-PredictionUnrolled Scheme
Hongshuai Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Shaping the interstage gain error in two-step oversampling ADCs has demonstrated a decent error suppression with a variety of mechanisms. The intersta
University of Macau, Macau, China
ISSCC 2023 Session 10 Data Converters
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer
Zongnan Wang1, Lu Jie2, Zichen Kong1, Mingtao Zhan2, Yi Zhong2, Yuan Wang1, Xiyuan Tang1
good energy efficiency. Lately, the incremental ADC is drawing rising attention by favoring system integration with its easy multiplexing and simple digital filtering. By combining a low-power SAR with a low-distortion ∆
Peking University, Beijing, China, 2Tsinghua University, Beijing, Chin
ISSCC 2023 Session 10 Data Converters
A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping
Yanbo Zhang*1,2, Junyan Hao1,2, Shubin Liu2, Zhangming Zhu2, Yan Zhu1,
Chi-hang Chan*1, R. P. Martins1,3 University of Macau, Macau, China Xidian University, Xi’an, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal *Equally Credited Authors (ECAs) 1 2 Emerging wirele
ISSCC 2023 Session 11 Power Management
A Scalable Heterogeneous Integrated Two-Stage Vertical Power-Delivery Architecture for High-Performance Computing
Casey Hardy1, Hieu Pham1, Mohamed Mehdi Jatlaoui2, Frederic Voiron2,
computing needs in data center, autonomous vehicle, and mobile device processors demand increasingly large peak currents at scaled-CMOScompatible voltages (<1V). To ease otherwise high I2R losses in power delivery (PD),
Tianshi Xie1, Po-Han Chen1, Saket Jha1, Patrick Mercier1, Hanh-Phuc Le
ISSCC 2023 Session 11 Power Management
A 12V-Input 1V–1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter
Wen-Liang Zeng1,2, Guigang Cai1, Chon-Fai Lee1, Chi-Seng Lam1, Yan Lu1,
Sai-Weng Sin1, Rui P. Martins1,3 University of Macau, Macau, China Zhuhai UM Science & Technology Research Institute, Zhuhai, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 A high-efficienc
ISSCC 2023 Session 11 Power Management
A 12V-to-1V Quad-Output Switched-Capacitor Buck Converter with Shared DC Capacitors Achieving 90.4% Peak Efficiency and 48mA/mm3 Power Density at 85% Efficiency
Tingxu Hu1, Mo Huang1, Yan Lu1, Rui P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Direct 12V-to-1V power delivery has become popular in datacenter applications. Multiple outputs regulated by switching regulators are favorable to red
University of Macau, Macau, China
ISSCC 2023 Session 11 Power Management
A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost
Suhwan Kim1, Harish K. Krishnamurthy1, Sergey Sofer2, Sheldon Weng1,
Shahar Wolf2, Ashoke Ravi1, Krishnan Ravichandran1, Ofir Degani2, James W. Tschanz1, Vivek De1 Intel, Hillsboro, OR Intel, Haifa, Israel 1 2 Power delivery components are critical for meeting size and weight requirements
ISSCC 2023 Session 11 Power Management
A Double Step-Down Dual-Output Converter with Cross Regulation of 0.025mV/mA and Improved Current Balance
Wei-Chieh Hung1, Cheng-Wen Chen1, Yu-Wei Huang1, An Chen1,
Zhen-Yu Yang1, Ke-Horng Chen1, Kuo-Lin Zheng1,2, Ying-Hsi Lin3, Shian-Ru Lin3, Tsung-Yen Tsai3, Wei-Cheng Huang1 National Yang Ming Chiao Tung University, Hsinchu, Taiwan 2 Chip-GaN Power Semiconductor, Hsinchu, Taiwan 3
ISSCC 2023 Session 11 Power Management
A 21W 94.8%-Efficient Reconfigurable Single-Inductor Multi-Stage Hybrid DC-DC Converter
Casey Hardy, Hanh-Phuc Le
The ongoing demand for smaller form factors and faster charging times of mobile products continue to drive the need for efficient, high-density power delivery (PD) for charging with a wide input voltage (VIN) range of 5V
University of California, San Diego, CA
ISSCC 2023 Session 11 Power Management
A 42W Reconfigurable Bidirectional Power Delivery Voltage-Regulating Cable
Zhiguo Tong1, Junwei Huang1, Yan Lu1, Rui P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 The universal serial bus (USB) has become really universal in recent years, with power delivery and all kinds of data protocols connected through a si
University of Macau, Macau, China
ISSCC 2023 Session 11 Power Management
A Wide 0.1-to-10 Conversion-Ratio Symmetric Hybrid Buck-Boost Converter for USB PD Bidirectional Conversion
Cheng Lin1, Chieh-Sheng Hung1, Si-Yi Li1, Ya-Ting Hsu1, Ke-Horng Chen1,
Semiconductor, Hsinchu, Taiwan 1 2 In recent years, USB Power Delivery (USB PD) is playing an increasingly important role in the field of consumer electronics. The USB PD 3.1 extends the delivering voltage up to 48V, whi
Kuo-Lin Zheng1,2, Ying-Hsi Lin3, Shian-Ru Lin3, Tsung-Yen Tsai3 Nation
ISSCC 2023 Session 11 Power Management
A 5A 94.5% Peak Efficiency 9~16V-to-1V Dual-Path Series-Capacitor Converter with Full Duty Range and Low V·A Metric
Xu Yang, Linhu Zhao, Menglian Zhao, Zhichao Tan, Yong Ding, Wuhua Li, Wanyuan Qu
ratio, high efficiency and compact 12V-to-1V DC-DC converters become increasingly important. Double step-down (DSD) converters [1–2], also known as series-capacitor converters, offer a promising solution using the capaci
Zhejiang University, Hangzhou, China As the power demand of computing
ISSCC 2023 Session 11 Power Management
A Compact 12V-to-1V 91.8% Peak Efficiency Hybrid Resonant Switched-Capacitor Parallel Inductor (ReSC-PL) Buck Converter
Guigang Cai1, Yan Lu1, Rui P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 High power density, high efficiency, and high voltage conversion ratio (VCR) DC-DC converters are in great demand for portable devices and autonomous
University of Macau, Macau, China
ISSCC 2023 Session 12 RF & Wireless
A 0.96pJ/b 7×50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies
Mayank Raj1, Chuan Xie1, Ade Bekele1, Adam Chou1, Wenfeng Zhang1,
Ying Cao1, Jae Wook Kim1, Nakul Narang2, Hongyuan Zhao2, Yipeng Wang2, Kee Hian Tan2, Winson Lin1, Jay Im1, David Mahashin1, Santiago Asuncion1, Parag Upadhyaya1, Yohan Frans1 AMD, San Jose, CA AMD, Singapore, Singapore
ISSCC 2023 Session 12 RF & Wireless
A 7 pA/√Hz Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS
Kadaba Lakshmikumar*1, Alexander Kurylak*1, Romesh Kumar Nandwana*1,
amplifier (TIA) is a critical building block that impacts the noise, bandwidth, and power consumption of intensity modulation and direct detection (IMDD) optical links used in data centers. CMOS TIAs using the shunt-feed
Bibhu Das1, Joe Pampanin1, Mike Brubaker1, Pavan Kumar Hanumolu2 CISCO
ISSCC 2023 Session 12 RF & Wireless
A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver
Ahmed E. Abdelrahman1, Mostafa G. Ahmed1,2, Mahmoud A. Khalil1,
increasing intra-datacenter traffic is pushing the demand for ultra-high-speed optical interconnect that maximizes both power efficiency and data rate per wavelength. Intensity modulation-direct detection (IM-DD) links a
Mohamed Badr Younis1, Kyu-Sang Park1, Pavan Kumar Hanumolu1 University
ISSCC 2023 Session 13 AI / ML
Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating the maximum frequency. Energy for inference (MNIST) using only the CPU memory and the core is 1681.97µJ, whereas energy for inference using the ACC is 0.19µJ. The inference time is reduced from 3.55s to 485µs. Therefore, our ACC enables inference according to the frame rate of imaging data (e.g., 60fps and 16ms).
Yuto Yakubo1, Kazuma Furutani1, Kouhei Toyotaka1, Haruki Katagiri1,
Masashi Fujita1, Munehiro Kozuma1, Yoshinori Ando1, Yoshiyuki Kurokawa1, Toru Nakura2, Shunpei Yamazaki1 The effect of power reduction when performing context switching and PG is compared between an OS/Si chip and a Si (
ISSCC 2023 Session 13 Other
A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring
a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature, Extractor and an RNN Classifier
Jinhai Lin1, Ka-Fai Un1, Wei-Han Yu1, Pui-In Mak1, Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Real-time speech recognizers and translators re
ISSCC 2023 Session 13 Other
A Triturated Sensing System
Noriyuki Miura1, Kotaro Naruse1, Jun Shiomi1, Yoshihiro Midoh1,
evolution of our information society today, where compact high-performance computers exist everywhere to provide us easy and immediate access to powerful information technologies and services. To further advance our info
Tetsuya Hirose1, Takaaki Okidono2, Takuji Miki2, Makoto Nagata2 Osaka
ISSCC 2023 Session 13 Other
A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication
Kotaro Naruse, Takayuki Ueda, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura
Ambient energy harvesting exploits existing energy for powering ICs and has been expanding operation space and application field of IC electronics. If an existing high energy source yet unexploited by ICs could be found,
Osaka University, Suita, Japan
ISSCC 2023 Session 13 Other
Subtractive Photonic Waveguide-Coupled Photodetectors in 180nm Bulk CMOS
Craig Ives, Ali Hajimiri
The integration of electronics and photonics into a single silicon CMOS process can serve wide-ranging applications, e.g. complex imaging and projection photonic systems, onchip optical interconnects, or self-correcting
California Institute of Technology, Pasadena, CA
ISSCC 2023 Session 13 Other
A Silicon Photonic Reconfigurable Optical Analog Processor (SiROAP) with a 4x4 Optical Mesh
Md Jubayer Shawon, Vishal Saxena
As we envision post-Moore solid-state circuits, there is a growing impetus for leveraging emerging device technologies outside the traditional CMOS fold. Silicon photonics (SiP) fabrication in CMOS-compatible foundries h
University of Delaware, Newark, DE
ISSCC 2023 Session 14 Digital Circuits
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur
Qiaochu Zhang1, Hsiang-Chun Cheng1, Shiyu Su1,2, Mike Shuo-Wei Chen1
University of Waterloo, Waterloo, Canada 1 2 Ring-oscillator (RO)-based injection-locked phase-locked loops (IL-PLLs) and multiplying delay-locked loops (MDLLs) are promising candidates for low-cost, highperformance cloc
University of Southern California, Los Angeles, CA
ISSCC 2023 Session 14 Digital Circuits
A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration
Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong,
generators to satisfy diverse specifications for different modules, such as microprocessors, memories, I/O interfaces, and power management. Conventionally, multiple PLLs are used in SoCs to provide various frequency out
Zhihua Wang, Baoyong Chi Tsinghua University, Beijing, China Modern sy
ISSCC 2023 Session 14 Digital Circuits
A Digital Low-Dropout (LDO) Linear Regulator with Adaptive Transfer Function Featuring 125A/mm2 Power Density and Autonomous Bypass Mode
Michael Zelikson, Kosta Luria, Lior Gil, Yuval Brown, Vadim Goldenbeg,
grouped and share a common power supply per group. A combination of a common supply with per-domain DVFS implies a need for local voltage regulation, which in some SOCs is based on LDOs. Operation conditions feature dyna
Dor Kasif, Elias Hlees, Alex Vinichuk Intel, Haifa, Israel Modern CPUs
ISSCC 2023 Session 15 Hardware Security
A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber
Xinjian Liu1, Daniel S. Truesdell1, Omar Faruqe1, Lalitha Parameswaran2,
Michael Rickley2, Andrew Kopanski2, Lauren Cantley2, Austin Coon2, Matthew Bernasconi2, Tairan Wang2, Benton H. Calhoun1 University of Virginia, Charlottesville, VA MIT Lincoln Laboratory, Lexington, MA 1 2 Rapid reducti
ISSCC 2023 Session 15 Hardware Security
A 2.19µW Self-Powered SoC with Integrated Multimodal
Energy Harvesting, Dual-Channel up to -92dBm WRX and, Energy-Aware Subsystem
Everactive, Charlottesville, VA, 2Everactive, Santa Clara, CA, 3Everactive, Ann Arbor, MI preserved. The SoC is designed to operate near-threshold to achieve its low power floor. Thus, an AVFS block is included to improv
ISSCC 2023 Session 15 Hardware Security
A 33kDMIPS 6.4W Vehicle Communication Gateway Processor
Achieving 10Gbps/W Network Routing, 40ms CAN Bus, Start-Up and 1.4mW Standby Power
in the Control domain can start the CAN service in parallel with booting for other (nonCAN) services. Moreover, decryption by a secure CPU and data loading from external memory can be performed in parallel by double buff
ISSCC 2023 Session 15 Hardware Security
A 28nm 68MOPS 0.18µJ/Op Paillier Homomorphic Encryption Processor with Bit-Serial Sparse Ciphertext Computing
Guiming Shi1, Zhanhong Tan1, Dapeng Cao2, Jingwei Cai1, Wuke Zhang3,
of tremendous emerging information applications, providing various reliable and high-performance services based on vast amounts of individual and organizational data. Paillier homomorphic encryption (PHE)
Yifu Wu3, Kaisheng Ma1 Tsinghua University, Beijing, China Xi’an JiaoT
ISSCC 2023 Session 15 Hardware Security
A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS
Raghavan Kumar1, Avinash Varna2, Carlos Tokunaga1, Sachin Taneja1,
from cryptographic engines to extract secret keys. A single fault injected into the penultimate AES round using directed laser pulses or voltage/clock glitches corrupts 4 output bytes (Fig. 15.5.1), reducing key search s
Vivek De1, Sanu Mathew1 Intel, Hillsboro, OR Intel, Chandler, AZ 1 2 F
ISSCC 2023 Session 16 AI / ML
MulTCIM: A 28nm 2.24µJ/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers
Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu,
natural language, speech, etc. Multimodal Transformer (MulT, Fig. 16.1.1) models introduce a cross-modal attention mechanism to vanilla transformers to learn from different modalities, achieving excellent results on mult
Shaojun Wei, Shouyi Yin Tsinghua University, Beijing, China Human perc
ISSCC 2023 Session 16 AI / ML
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine
Shiwei Liu1, Peizhe Li1, Jinshan Zhang1, Yunzhengmao Wang1, Haozhe Zhu1,
Transformer networks, from BERT, GPT to Alphafold, have demonstrated unprecedented advances in a variety of AI tasks. Fig. 16.2.1 shows the computing flow of self-attention – the fundamental operation in transformers. Qu
Wenning Jiang1, Shan Tang2, Chixiao Chen1,3, Qi Liu1, Ming Liu1 Fudan
ISSCC 2023 Session 16 Digital Processors
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture
Jinshan Yue1, Chaojie He1, Zi Wang1, Zhaori Cong1, Yifan He2, Mufeng Zhou2,
University, Beijing, China 1 2 Computing-in-memory (CIM) has shown high energy efficiency on low-precision integer multiply-accumulate (MAC) [1-3]. However, implementing floating-point (FP) operations using CIM has not b
Wenyu Sun2, Xueqing Li2, Chunmeng Dou1, Feng Zhang1, Huazhong Yang2, Y
ISSCC 2023 Session 16 Digital Processors
TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration
Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu,
Recommendation Models (DLRMs) have computational and data-movement requirements beyond those seen in typical NN processing. Such beyond-NN applications typically consist of Sparse Gathering (SpG) and Sparse Algebra (SpA)
Shaojun Wei, Shouyi Yin Tsinghua University, Beijing, China Applicatio
ISSCC 2023 Session 16 Digital Processors
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching
Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha,
and area efficiency for deep neural network (DNN) processing [1-3]. As shown in Fig. 16.5.1, despite promising macro-level efficiency and throughput, there remain three main challenges to extending gains to system perfor
Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo Korea Advanced
ISSCC 2023 Session 16 AI / ML
A Nonvolatile AI-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W
Wei-Hsing Huang*1, Tai-Hao Wen*1,2, Je-Min Hung*1, Win-San Khwa*2,
Yun-Chen Lo1, Chuan-Jia Jhang1,2, Hung-Hsi Hsu1, Yu-Hsiang Chin1, Yu-Chiao Chen1, Chung-Chuan Lo1, Ren-Shuo Liu1, Kea-Tiong Tang1, Chih-Cheng Hsieh1, Yu-Der Chih3, Tsung-Yung Chang3, Meng-Fan Chang1,2 National Tsing Hua
ISSCC 2023 Session 16 AI / ML
A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications
Giuseppe Desoli*1, Nitin Chawla*2, Thomas Boesch*3, Manuj Ayodhyawasi*2,
Harsh Rawat2, Hitesh Chawla2, Abhijith VS2, Paolo Zambotti4, Akhilesh Sharma2, Carmine Cappetta1, Michele Rossi1, Antonio De Vita1, Francesca Girardi1 STMicroelectronics, Cornaredo, Italy STMicroelectronics, Noida, India
ISSCC 2023 Session 17 Data Converters
A 2×-Interleaved 9b 2.8GS/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input
Hongzhi Zhao1, Minglei Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 By increasing the number of bits in each conversion cycle, the sampling rate of SAR ADCs can be considerably extended while maintaining superior energ
University of Macau, Macao, China
ISSCC 2023 Session 17 Data Converters
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with 2× Interpolating Sense-Amplifier-Latches
Abdullah Serdar Yonar1,2, Pier Andrea Francese1, Matthias Brändli1,
2 Circuit innovations in medium-low resolution ADCs are among the key enablers to achieving higher data rates, currently at 224Gb/s [1], in the next-generation datacommunication links based on sophisticated DSP technique
Marcel Kossel1, Mridula Prathapan1, Thomas Morf1, Andrea Ruffino1, Tae
ISSCC 2023 Session 17 Data Converters
A 14b 16GS/s Time-Interleaving Direct-RF Synthesis DAC with T-DEM Achieving -70dBc IM3 up to 7.8GHz in 7nm
Wei-Hsin Tseng*1, Willy Lin*1, Chung-Wei Hsu1, Chang-Yang Huang1,
Yu-Sian Lin1, Hung-Yi Huang1, HsinWei Chen1, Sheng-Hui Liao1, Kuan-Dar Chen1, Jon Strange2, Gabriele Manganaro3 MediaTek, HsinChu, Taiwan, 2MediaTek, Kent, United Kingdom, 3MediaTek, Woburn, MA *Equally Credited Authors
ISSCC 2023 Session 17 Data Converters
A 750mW 24GS/s 12b Time-Interleaved ADC for Direct RF Sampling in Modern Wireless Systems
Sandeep Santhosh Kumar1, Masahiro Kudo1, Vlad Cretu1, Antoine Morineau1,
Atsushi Matsuda2, Minori Yoshida2, Masazumi Marutani2, Aadil Hussain Maniyar1, Jay Kumar1 Socionext Europe, Maidenhead, United Kingdom Socionext, Yokohama, Japan 1 2 An ADC with a sampling rate of tens of GS/s and a high
ISSCC 2023 Session 17 Data Converters
A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor
Mingtao Zhan, Lu Jie, Nan Sun
Next-generation wireless standards (e.g., WiFi-7) advancing towards wider bandwidth and higher order modulation require ADCs with GHz sampling rates and over 12b resolution. Although conventional pipelined ADCs can satis
Tsinghua University, Beijing, China