A 0.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms

📋 论文概要

该论文提出了一种工作在0.4V超低电源电压下的锁相环（ULV-SS-PLL），通过创新的电路设计同时实现了低功耗、低抖动和低参考杂散，适用于物联网等电池供电或免电池应用。

💡 主要创新点

• 采用超低电压（0.4V）供电的锁相环架构，显著降低功耗并支持电池寿命延长。
• 实现了236.6fsrms的集成抖动、-253.8dB的抖动功耗优值（FoM）以及-76.1dBc的参考杂散，综合性能优异。

🏷 关键词

📄 原文摘要

Zhao Zhang1, Xinyu Shen1, Zhaoyu Zhang1, Guike Li1, Nan Qi1, Jian Liu1, Yong Chen2, Nanjian Wu1, Liyuan Liu1 Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China University of Macau, Macau, China 1 2 Scaling down supply voltage (VDD) to sub-0.4V is tremendously attractive for the internetof-things (IoT) applications, which offers a great benefit to extending the lifetime of IoT devices or enabling batteryless operation [1]. Furthermore, tailoring an ultra-low-voltage (ULV) phase-locked loop (PLL) to simultaneously lower power consumption, integrated jitter, and reference (REF) spur is highly desirable, especially for IoT radios. Several LCbased ULV-PLLs have been reported, e.g., all-digital PLL (AD-PLL) [1], charge-pump-based PLL (CP-PLL) [2], and XOR-gate-based PLL (XOR-PLL) [3]. Yet, the limited resolution of the time-to-digital converter in the AD-PLL, and the poor CP

👥 作者与机构

Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference, Spur