技术领域

Clocking & PLLs

127 篇相关论文 (2008–2026)

ISSCC 2026 Session 27 Clocking & PLLs
A Dual-Mode DCO-PA with a Twisted 8-Shape Inductor for BLE Achieving 42% TX Efficiency at 1.6dBm and 0.29mW RX Clock
Jiawen Chen1,2, Kai Xu2, Luyi Guo1, Teerachot Siriburanon1, Jun Yin3, Bashir M. Al-Hashimi2, Robert Bogdan Staszewski1
Abstract This paper presents a 0.3V dual-mode (2.4/4.8GHz) DCO-PA for BLE, achieving 42% efficiency in the TX mode and 0.29mW power consumption in the RX clock mode. It features: 1) a twisted 8-shape inductor enabling oc
University College Dublin, Dublin, Ireland, 2King’s College London, Lo
ISSCC 2026 Session 27 Clocking & PLLs
A 77GHz 8-bit CMOS Phase Shifter Adopting a Nested-Vector-Based Error Correction with 0.33°/0.07dB RMS-Error for MIMO Radar Applications
Geonho Park, Byeong-Taek Moon, Kyunghwan Kim, Doyoon Kim, Goeun Baek, Byungho Yook, Hyun-Chul Park, Chan-Hong Park
Abstract In this paper, we present a 77GHz 8-bit nested vector-sum phase shifter in 28nm CMOS. The architecture performs vector modulation by splitting a single outer vector into two inner vectors generated by a two-stag
Samsung Electronics, Hwaseong, Korea
ISSCC 2026 Session 27 Clocking & PLLs
A 40.5-to-58.5GHz 36%-Fractional-Chirp-Bandwidth 18GHz-Absolute-Chirp-Bandwidth 2.2GHz/μs-Chirp-Rate 0.02%-Chirp-Error Post-Mixing Bandwidth-Extending Sawtooth-FMCW Frequency Synthesizer Employing a Chirp-Tracking ILFT and a Fractional-Bandwidth Doubler
Yi Liu*, Zixi Jing*, Wen Yang, Hanlin Yang, Bodong Zhang, Howard Cam Luong
*Equally Credited Authors (ECAs) Abstract An 18GHz-bandwidth (BW) sawtooth-FMCW synthesizer is presented. First, a chirp-tracking ILFT with feed-forward and frequency-tracking loop ensures robust and continuous tracking
HKUST, Hong Kong, China
ISSCC 2026 Session 27 Clocking & PLLs
A 9.7GHz Self-Linearized-VCO-Based FMCW Chirp Generator Achieving 1.56GHz/μs Slope and 0.57μs Duration with 0.094% rms Frequency Error
Daxu Zhang, Yuncheng Zhang, Zezheng Liu, Yuang Xiong, Michele Rossoni, Wenqian Wang, Ashbir Aviat Fadila, Duo Li, Minzhe
7GHz self-linearized-VCO-based Type-III FMCW synthesizer is presented. A CCal bank calibrates the nonlinearity of the CMod bank, and two LMS-based calibrations (gain and offset) reduce digital overhead and ensure stable
Carrel de Gomez, Dingxin Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Kenichi
ISSCC 2026 Session 27 Clocking & PLLs
A 0.068mm2 8.5-to-12.7GHz Complementary Dual-Core VCO with Auto-2nd-Harmonic-Tracking Technique Achieving 202.7dBc/Hz Peak FoMT and 0.9dB-FoM Variation at a 1MHz Offset in a 39.6% Tuning Range
Xincheng Du1,2, Xiangxun Zhan1, Tincheng Ou1, Zaize Chen1, Jinge Li1, Haoran Li1, Zhizhan Yang3, Zhuo Xu1, Pui-In Mak1,
Abstract A complementary dual-core VCO with auto f2nd tracking is proposed to achieve consistently low PN and a high FoM over a wide tuning range (TR). Prototyped in 65nm CMOS, the proposed VCO achieves a peak FoM@1/10MH
University of Macau, Macau, China, 2UM Hetao IC Research Institute, Sh
ISSCC 2026 Session 27 Clocking & PLLs
A 14GHz Ring-Based 3rd-Order Fractional-N PLL with 164fsrms Jitter and a 100MHz Reference
Zhaochen Zhu, Qingxuan Lin, Zhiqiang Huang
Abstract This work presents a 14GHz ring-based 3rd-order fractional-N PLL with 164fsrms jitter and a 100MHz reference. A sub-sampling DLL is cascaded in the type-II PLL output for extra phase-noise and supply-noise suppr
Hong Kong University of Science and Technology, Guangzhou, China
ISSCC 2026 Session 27 Clocking & PLLs
÷ Nint AUX RO Non-overlapping Clock Generator + - + CBaux[2:0] + - + + - Vref Vb Vo V+ + Gm FFNC On: 157 fs Fractional-N Mode 60MHz × 52 ÷ 30 × 31 × 2 (c) Vctrlmain 60MHz × 52 ÷ (30+2-13) × (31+2-13) × 2 6.7GHz (d) fout 6.2~6.8GHz - α[k] MMD-based Q-Noise Cancellation FFNC On: 145 fs Integer-N Mode Feedforward RO Noise Cancellation UGB V- ÷ Nmain FFNC Off: 357 fs + - ÷ Naux α 6.4GHz FFNC Off: 358 fs L1: 382 pH L2: 421 pH Vctrlaux AUX Integer-N SPLL (fBW1 = 10MHz) faux 3.1~3.4GHz (b) Frac. Spur ×7 Main LCO Gm MASH 1-1-1 6.4GHz Vctrlaux + - + AUX/Main SPDs with identical design (a) OUT+ IN- CBaux[2:0] fref 60MHz OUT- IN+ Frac. Spur 6.7GHz QEC Off FFNC Off: 442 fs Vref fmain 100~160MHz Vin1 fdiv2 3.1~3.4GHz CBmain[4:0] Vout Vin2 Main Fractional-N SPLL (fBW2 = 1MHz) ÷2 Figure 27.2.3: Circuit implementation of the proposed PLL. (a) Fractional-N Mode 60MHz × 53 ÷ (20+2-11) × (21+2-11) × 2 fBW2 fBW1 Main PLL PN FFNC On Naux x 1 Naux x 1.5 Naux x 2 fref/2 (d) α=2-10 α=2-9 -84.7dBc (-72.7dBc) 203kHz 102kHz -84.8dBc (-72.8dBc) 60MHz × 53 ÷ 20 × (21+2-11) × 2 This Work H. Zhang ISSCC'25 D. Yang ISSCC'22 SPD/SPD D. Xu JSSC'25 Pulse Gen. +BBPD G. Jin JSSC'24 M. Mercandelli JSSC'22 W. Wu JSSC'21 SPD SPD SPD Phase Detector Noise Cancell./ Filter. Technique Calibration required? SPD/PFDCP SPD/XORPD MMD-QEC +FFNC MMD-QEC Harmonicmixing DTC-QEC DTC-QEC DTC-QEC DTC-QEC No No No Yes Yes Yes Yes VCO Type Ring+LC LC+LC LC+LC Ring+LC LC LC LC 60 82 74 50 100 500 76.8x2 6.2 to 6.8 4.7 to 5.7 25 to 28 6.5 to 8 3.3 to 4.5 11.9 to 14.1 5 to 7 157 (1k to 100M) 95.9 (1k to 100M) 88 (10k to 40M) 191 (10k to 10M) 203 (10k-100M) 58.2 (1k-100M) 80~95 (10k-100M) %72.7 %70.6 %70 %52.7 %57 %63.2 <%72 Reference Frequency [MHz] Output Frequency [GHz] (c) Fractional-N Mode Figure 27.2.4: Measured PN near 6.4GHz in (a) integer-N mode and (b) fractional-N mode with QEC on, FFNC on or off; measured PN near 6.7GHz in (c) fractional-N mode with QEC on, FFNC on or off and (d) fractional-N mode with FFNC on, QEC on or off. (b) RO, AUX PLL PN Normalized to Main PLL Freq. Main PLL PN FFNC Off FFNC On: 160 fs ×31 Non-overlapping Clock Generator Integrated Jitter [fs] In-band Fractional Spur [dBc] Power [mW] 17.2 21.2 12.9 14.2 2.4 18 14.2 FoM* [dB] %243.7 %247.1 %250 %242.9 %250.0 %252.1 %250.4 ~ %249.0 FoMREF** [dB] %235.9 %238.0 %241.3 %235.9 %240.0 %235.1 %241.5 ~ %240.1 CMOS Process [nm] Active 2 Area [mm ] 65 65 7 65 40 28 14 0.16 0.25 0.24 0.48 0.36 0.16 0.31 Figure 27.2.5: (a) FFNC robustness verification based on measurement results; (b) *FoM = 10log((Power/1mW)*(Jitter/1s)2) **FoMref = 10log((Power/1mW)*(Jitter/1s)2)+10log(fref/10MHz) measured fractional spur levels at near-integer channels; (c)(d) measured output Figure 27.2.6: Performance comparison of the proposed PLL with prior-art designs. spectra with fractional spurs. Power (mW) AUX 0.9 5% Loop RO 5.8 34% Main 1.7 10% Loop DSM 0.4 2% LCO 8.4 49% Total 17.2 100% 850μm 480μm LCO Main LF FFAMP AUX SPD/Div. AUX GM /LF AUX/Main MMDs DSM Main SPD/GM RO Area (mm2) AUX 0.010 6% Loop RO 0.006 4% Main 0.023 14% Loop DSM 0.003 2% LCO 0.119 74% Total 0.162 100% Figure 27.2.7: Die micrograph (left); measured power consumption and area (right). • 2026 IEEE International Solid-State Circuits Conference 979-8-3315-8936-3/26/$31.00 ©2026 IEEE
ISSCC 2026 Session 27 Clocking & PLLs
A 48-to-82.5GHz CMOS Split-Tail Gilbert-Cell Frequency Doubler Achieving 11% PAE at 8.5dBm Output Power
Jismal Jamal1, Lorenzo Piotto2, Federico Vecchi3, Mahmoud M. Pirbazari3, Andrea Mazzanti1
Abstract A 48-to-82.5GHz frequency doubler in 28nm FDSOI CMOS using a modified Gilbert cell is presented. The tail transconductors are split and the switching-quad transistors AC-shorted by capacitors. DC offset builds u
University of Pavia, Pavia, Italy, 2Fondazione Chips-IT, Pavia, Italy,
ISSCC 2026 Session 27 Clocking & PLLs
A 20GHz Frequency Synthesizer with Spur-Shaping Modulator Achieving 46.2fs Jitter and -76.5dBc Worst-Case Fractional Spur
Zonglin Ye, Yuxuan Sun, Longxiang Hou, Yuhan Ding, Yixuan Wen, Hongyang Zhang, Xinlin Geng, Qian Xie, Shiheng Yang, Zhen
Abstract In this paper, a frequency synthesizer is proposed with low fractional spur and low jitter, featuring a spur-shaping-modulator (SSM) technique that suppresses the nonlinearity arising from inter-slice mismatch.
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2026 Session 12 Clocking & PLLs
A 5.7mW@0.55V-to-50mW@0.9V Deeply Power-Scalable Reconfigurable Series-Resonance/Class-F VCO with Mutual-Inductance Self-Cancellation and Hybrid 8-Shaped Coupling Techniques
Juntao Lan, Wei Deng, Haikun Jia, Shiwei Zhang, Zhihua Wang, Baoyong Chi
Abstract This work presents a 28nm deeply power-scalable reconfigurable series-resonance/ClassF VCO with mutual-inductance self-cancellation and hybrid 8-shaped coupling techniques, achieving power scalability from 5.7 t
Tsinghua University, Beijing, China
ISSCC 2026 Session 12 Clocking & PLLs
A 7.15-to-7.95GHz Magnetically Enhanced Feedforward Waveform-Shaping CMOS Oscillator with Implicit Common-Mode Noise Cancellation Achieving -146.72dBc/Hz PN@1MHz and 190.6dBc/Hz FoM
Rui Ma, Wei Deng, Haikun Jia, Juntao Lan, Zhihua Wang, Baoyong Chi
Abstract Pure microwave sources are vital for precision instrumentation, but conventional schemes are bulky and costly. CMOS oscillators are inexpensive and compact yet limited by phasenoise performance. To address this,
Tsinghua University, Beijing, China
ISSCC 2026 Session 12 Clocking & PLLs
A 0.65-to-1V-VDD 10.5-to-11.85GHz Fractional-N Sampling PLL Achieving 71.47fs Integrated Jitter and <-60dBc Near-Integer Fractional Spur in 40nm CMOS
Yixi Li1,2, Junjie Chen1,2, Xinyu Shen1, Jie Yang3, Jian Liu1,2, Nanjian Wu1,2, Zhao Zhang1,2, Liyuan Liu1,2
Abstract This paper presents a 0.65-to-1V, 10.5-to-11.85GHz wide-VDD-range (WV) fractional-N sampling PLL. The QE-reduction WV SPD, high-linearity 2-stage DTC, and DCC-aided QE dithering method are proposed to address th
Institute of Semiconductors, Chinese Academy of Sciences, Beijing, Chi
ISSCC 2026 Session 12 Clocking & PLLs
A 14GHz Chopper-Refolding Sampling PLL Achieving 33.8fsrms and 80.8dBc Reference Spur with a kT/C-Noise-Cancellation SPD
Yichen Liu, Jian Zhang, Xiaosen Liu, Yan Wang
Abstract A 14GHz chopper-refolding sampling PLL is implemented in 28nm CMOS, integrating a kT/C-noise-cancellation sampling phase detector (SPD) and a self-injection VCO with harmonic-impedance expansion. The SPD decoupl
Tsinghua University, Beijing, China
ISSCC 2026 Session 12 Clocking & PLLs
A –66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC
Pietro Salvi, Michele Rossoni, Riccardo Moleri, Daniele Lodi Rizzini, Damiano Fagotti, Stefano Gallucci, Andrea Leonardo
inverse-constant-slope DTC for rejection of supply disturbances is presented. Compared to traditional fractional-N digital PLLs, it requires no additional calibration for supply rejection or additional supply-insensitive
Politecnico di Milano, Milan, Italy Abstract A fractional-N digital PL
ISSCC 2026 Session 12 Clocking & PLLs
A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving –62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mVrms DTC Supply Noise
Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, Giovanni Rocco
variable-slope digital-to-time converter (DTC) is presented. Supply insensitivity is achieved by a background calibration loop, without affecting DTC linearity or noise. Measured results demonstrate 65.6fs jitter upon 6.
Simone Mattia Dartizio, Salvatore Levantino Politecnico di Milano, Mil
ISSCC 2025 Session 19 Clocking & PLLs
A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL
Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61dBc, In-band Fractional Spur in 40nm CMOS
stage DPD is implemented digitally. Thanks to its cascaded structure, our HC-DPD with a 6b calibration coefficient can be split into two-stage 3b DPDs, enabling significant hardwareoverhead reduction compared to the conv
ISSCC 2025 Session 19 Clocking & PLLs
A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fsrms
Jitter, -249.7dB FoM, and 1.98µs Locking Time Using a, Polarity-Reversible SSPD
Haoran Li1, Jinge Li1, Xueying Jiang1, Xi Meng1, Jun Yin1, Rui P. Martins1,2, Pui-In Mak1 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Millimeter-wave (mm-wave)
ISSCC 2025 Session 19 Clocking & PLLs
A 60GHz I/Q-Calibrated SSB-Mixer-Based LO with Sub-ns Settling Time and -56dBc Worst-Case Spur Using ILO Filter in 28nm CMOS
Jaewon Oh1, Cheol So2, Hyojun Kim3, Songcheol Hong1, SeongHwan Cho1
University of California, Santa Babara, CA 3 Korea Aerospace Research Institute, Daejeon, Korea 1 2 Joint communication and radar sensing (JCAS) has been gaining much attention for its efficient use of spectrum, particul
KAIST, Daejeon, Korea
ISSCC 2025 Session 19 Clocking & PLLs
A Differential Series-Resonance CMOS VCO with Pole-Convergence Technique Achieving 202.1dBc/Hz FoMTA at 10MHz Offset
Jinhua Guo, Pei Qin, Haoshen Zhu, Xiang Yi, Wenjie Feng, Wenquan Che, Quan Xue
sought for various applications, such as high-speed wireless/wireline communications, high-speed ADC/DACs, etc. According to Leeson’s formula (Fig. 19.5.1 top-left), achieving lower PN requires a larger VTANK or a smalle
South China University of Technology, Guangzhou, China Voltage-control
ISSCC 2025 Session 19 Clocking & PLLs
An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz
Jiawen Chen1, Kai Xu2, Teerachot Siriburanon1, Robert Bogdan Staszewski1
King’s College London, London, United Kingdom 1 2 As data-rate requirements in 5G-Advanced and future 6G communications continue to rise, an RF oscillator with ultra-low phase noise (PN) is a prerequisite for ensuring hi
University College Dublin, Dublin, Ireland
ISSCC 2025 Session 19 Clocking & PLLs
A Fractional-N PLL with 34fsrms Jitter and -255.5dB FoM Based on a Multipath Feedback Technique
Chao-Ching Hung, Chih-Hsien Shen, Chien-Li Lin, Mou Tzou, Kevin Fong, Yu-Li Hsueh
modulation schemes, such as 4K-QAM, and impose stringent phase-noise requirements on frequency synthesizers. In the past few years, an increasing number of frac-N PLLs with excellent jitter performance, i.e., sub-100fs,
MediaTek, Hsinchu, Taiwan State-of-the-art advanced-communication stan
ISSCC 2025 Session 19 Clocking & PLLs
A 13GHz Charge-Pump PLL Achieving 15.8fsrms Integrated Jitter and -98.5dBc Reference Spur
Depeng Sun1, Feng Bu1, Qixian Ye1, Shijie Li1, Yuan Gao1, Bowen Wang1, Hao Xu2,
wideband data converters, have imposed extremely stringent demands on phase-locked loops (PLLs) for lower jitter and spurs. Benefiting from high phase-detector (PD) gain, sub-sampling PLLs (SSPLLs) achieve superior jitte
Na Yan2, Shubin Liu1, Zhangming Zhu1 Xidian University, Xi’an, China F
ISSCC 2025 Session 19 Clocking & PLLs
A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving -255.2dB FoMJ Including the XO Power and Noise voltages as low as 0.28V for low-power VCO implementation, with the possibility to go up to 0.45V without risking gate-dielectric breakdown if lower out-of-band noise is needed. The performance of the VCO is further enhanced by the second-harmonic-resonance method applied at both supply and ground sides [18,19].
Can Livanelioglu*, Long He*, Jiang Gong*, Sina Arjmandpour, Gabriele Atzeni, Taekwang Jang
Figure 19.10.3 shows the details of the proposed pulse-injection XO driver and its noise characteristics. Figure 19.10.3 (left) shows the theoretical calculation and the simulation of the XO phase-noise (PN) floor (PNXO)
ISSCC 2025 Session 19 Clocking & PLLs
A PVT-Robust 5.5GHz Fractional-N Cascaded RO-Based Digital PLL with Voltage-Domain Feedforward Noise Cancellation
Yu Duan1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 Ring-oscillator (RO)-based digital PLLs (DPLLs) are well-suited for multi-PLL-integrated SoC designs owing to their compactness and immunity to magnetic
University of Macau, Macau, China
ISSCC 2024 Session 10 Clocking & PLLs
An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%
rms Frequency Error under a 2.3GHz Chirp Bandwidth,
2.3GHz/μs Slope, and 50ns Idle Time in 65nm CMOS Xuan Wang*1,2, Xujun Ma*3, Yupeng Fu1, Yuqian Zhou1, Ang Li1, Shuo Yang1, Xu Wu1,2, Dongming Wang1,2, Lianming Li1,2, Xiaohu You1,2 Southeast University, Nanjing, China Pu
ISSCC 2024 Session 10 Clocking & PLLs
A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
Francesco Tesolin*1, Simone Mattia Dartizio*1, Giacomo Castoro1,
Andrea Leonardo Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy Infineon Technologies, Villach, Austria *Equally Credited Authors (ECAs) 1 2 Improving the spatial resolution and reliability of target de
Francesco Buccoleri1, Michele Rossoni1, Dmytro Cherniak2, Carlo Samori
ISSCC 2024 Session 10 Clocking & PLLs
A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique
Yuhwan Shin*1,2, Junseok Lee*1,2, Juyeop Kim*1,2, Yongwoo Jo1,2, Jaehyouk Choi2
most popular architecture for generating ultralow-jitter signals due to their high-gain sampling phase detectors (SPDs) that can significantly reduce in-band phase noise (PN). However, to maintain this advantage even in t
Korea Advanced Institute of Science and Technology, Daejeon, Korea Seo
ISSCC 2024 Session 10 Clocking & PLLs
A 45.5fs-Integrated-Random-Jitter and -75dBc-IntegerBoundary-Spur BiCMOS Fractional-N PLL with Suppression
of Fractional, Horn, and Wandering Spurs
Michael Peter Kennedy1,2, Valerio Mazzaro1,2, Stefano Tulisi3, Micheál Scully3, Niall McDermott3, James Breslin3 University College Dublin, Dublin, Ireland Microelectronic Circuits Centre Ireland, Dublin, Ireland 3 Analo
ISSCC 2024 Session 10 Clocking & PLLs
A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter
Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang,
Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada Tokyo Institute of Technology, Tokyo, Japan Modern wireless transceivers and FMCW
ISSCC 2024 Session 10 Clocking & PLLs
An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM
Michele Rossoni*, Simone Mattia Dartizio*, Francesco Tesolin,
transceivers exploit high-order modulation schemes to increase datarates and call for high-spectral-purity frequency synthesizers. To serve this purpose, a fractional-N PLL that removes the time quantization error betwee
Giacomo Castoro, Riccardo Dell’Orto, Carlo Samori, Andrea Leonardo Lac
ISSCC 2023 Session 4 Clocking & PLLs
A 0.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms
Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference, Spur
Zhao Zhang1, Xinyu Shen1, Zhaoyu Zhang1, Guike Li1, Nan Qi1, Jian Liu1, Yong Chen2, Nanjian Wu1, Liyuan Liu1 Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China University of Macau, Macau, China 1 2
ISSCC 2023 Session 4 Clocking & PLLs
A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth
Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi
The W and D bands located at the lower boundary of the sub-THz spectrum are considered viable candidates for CMOS-based wireless-communication systems to utilize sub-THz frequencies. However, there are still many challen
Korea Advanced Institute of Science and Technology, Daejeon, Korea
ISSCC 2023 Session 4 Clocking & PLLs
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
Giacomo Castoro*1, Simone M. Dartizio*1, Francesco Tesolin1,
Carlo Samori1, Andrea L. Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy, 2Infineon Technologies, Villach, Austria *Equally Credited Authors (ECAs) 1 The quest of increasingly higher mobile uplink/down
Francesco Buccoleri1, Michele Rossoni1, Dmytro Cherniak2, Luca Bertule
ISSCC 2023 Session 4 Clocking & PLLs
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration constructed DAC voltage (VDAC) is shaped with a high slope (SDAC) in the gain-boosted PD, a high SDAC is achieved by generating a slope on VDAC in the gain-boosted PD, and the DTC delay is used to compensate for the timing error from CLKFB to the voltage crossing.
Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang,
Dingxin Xu, Hongye Huang, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany, Yuang Xiong, Atsushi Shirane, Kenichi Okada Figure 4.4.3 illustrates the proposed gain-boosted PD. In the conventional OSPLL, the slew rate of th
ISSCC 2023 Session 4 Clocking & PLLs
A 76.7fs-Integrated-Jitter and -71.9dBc In-Band FractionalSpur Bang-Bang Digital PLL Based on an Inverse-ConstantSlope DTC and FCW Subtractive Dithering
Simone M. Dartizio1, Francesco Tesolin1, Giacomo Castoro1,
Luca Bertulessi1, Carlo Samori1, Andrea L. Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milano, Italy, 2Infineon Technologies, Villach, Austria 1 Ultra-low-jitter and high-spectral-purity frequency synthesizers
Francesco Buccoleri1, Luca Lanzoni1, Michele Rossoni1, Dmytro Cherniak
ISSCC 2023 Session 4 Clocking & PLLs
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
Yongwoo Jo*, Juyeop Kim*, Yuhwan Shin, Chanwoong Hwang, Hangi Park, Jaehyouk Choi
bands are still the primary spectrum for 5G communications due to their natural advantages, such as higher compatibility/interoperability with existing networks and better properties for radio transmission. To fully util
Korea Advanced Institute of Science and Technology, Daejeon, Korea *Eq
ISSCC 2022 Session 23 Clocking & PLLs
A 68.6fsrms-Total-Integrated-Jitter and 1.56µs-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
Simone Mattia Dartizio*1, Francesco Buccoleri*1, Francesco Tesolin1,
Luca Avallone2, Alessio Santiccioli1, Agata Iesurum3, Giovanni Steffan2, Dmytro Cherniak2, Luca Bertulessi1, Andrea Bevilacqua3, Carlo Samori1, Andrea Leonardo Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan,
ISSCC 2022 Session 23 Clocking & PLLs
A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with -250dB FoM
Dihang Yang1, David Murphy1, Hooman Darabi1, Arya Behzad1, Asad Abidi2,
>25GHz inevitably faces the problems of a large closed-loop gain fvco/fref = N. Phase noise and spurs on the reference input and from other sources in the loop referred to its input are amplified by N. A narrow loop band
Stephen Au1, Sraavan Mundlapudi1, Kejian Shi1, Weiyu Leng2 Broadcom, S
ISSCC 2022 Session 23 Clocking & PLLs
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a TimeMode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs
Zhong Gao1, Jingchu He1, Martin Fritz2, Jiang Gong1, Yiyu Shen1, Zhirui Zong1,
Peng Chen3, Gerd Spalink2, Ben Eitel2, Ken Yamamoto4, Robert Bogdan Staszewski1,3, Morteza S. Alavi1, Masoud Babaie1 Delft University of Technology, Delft, The Netherlands Sony Europe, Stuttgart, Germany 3 University Col
ISSCC 2022 Session 23 Clocking & PLLs
A 188fsrms-Jitter and –243dB-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
Chanwoong Hwang*, Hangi Park*, Taeho Seong, Jaehyouk Choi
*Equally Credited Authors (ECAs) Modern SoCs for advanced wireless/wired applications integrate an increasing number of PLLs. 5G TRXs require multiple PLLs to implement complex schemes of carrier aggregation and MIMO. Mu
KAIST, Daejeon, Korea
ISSCC 2022 Session 23 Clocking & PLLs
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur
Tsung-Hsien Tsai1, Ruey-Bin Sheen1, Sheng-Yun Hsu1, Ya-Tin Chang1,
communications, require deep-subpicosecond integrated phase jitter [1]. Their in-band phase noise (PN) can be adversely affected by flicker noise and a large feedback frequency-division ratio, N. Cascaded PLLs are a rece
Chih-Hsien Chang1, Robert Bogdan Staszewski2 TSMC, Hsinchu, Taiwan Uni
ISSCC 2021 Session 32 Clocking & PLLs
A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
Alessio Santiccioli*1, Mario Mercandelli*1, Simone M. Dartizio*1,
Francesco Buccoleri1, Luca Avallone2, Angelo Parisi1, Dmytro Cherniak3, Andrea L. Lacaita1, Michael Peter Kennedy2, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milano, Italy University College Dublin, Dubl
Francesco Tesolin1, Saleh Karman1, Abanob Shehata1, Luca Bertulessi1,
ISSCC 2021 Session 32 Clocking & PLLs
A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth
Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian,
independent crystal oscillators (XOs): a 32.768kHz XO for the real-time clock (RTC) and a tens of MHz XO for low-jitter clock and carrier synthesis. To reduce the number of XOs, 32kHz-reference phase-locked loops (PLLs)
Hongye Huang, Yuncheng Zhang, Yun Wang, Atsushi Shirane, Kenichi Okada
ISSCC 2021 Session 32 Clocking & PLLs
A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS
Edwin Thaller1, Run Levinger2, Evgeny Shumaker2, Aryeh Farber2,
Sergey Bershansky2, Nir Geron2, Ashoke Ravi3, Rotem Banin2, Jasmin Kadry2, Gil Horovitz2, Christian Krassnitzer1, Christoph Duller1, Patrick Torta1, Mark Elzinga4, Kamran Azadet5 Intel, Villach, Austria Intel, Israel, Is
ISSCC 2021 Session 32 Clocking & PLLs
A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/µs Slope
Zhengkun Shen1, Haoyun Jiang1, Fan Yang1, Yixiao Wang2, Zherui Zhang1,
for millimeter-wave (mm-wave) frequency-modulated continuous-wave (FMCW) radars. Large-chirp-bandwidth (BWchirp) sawtooth waveforms are required to be synthesized with fast slope and high-frequency linearity for accurate
Junhua Liu1, Huailin Liao1 Peking University, Beijing, China Universit
ISSCC 2021 Session 32 Clocking & PLLs
A 104fsrms-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique
Juyeop Kim*1, Yongwoo Jo*1, Younghyun Lim*2, Taeho Seong2, Hangi Park1,
2 *Equally Credited Authors (ECAs) Subsampling PLLs (SSPLLs) are attractive architectures to generate ultra-low-jitter RF signals due to their intrinsically high phase-error-detection gain, KSH. However, this highgain op
Seyeon Yoo1, Yongsun Lee3, Seojin Choi1, Jaehyouk Choi1 KAIST, Daejeon
ISSCC 2021 Session 32 Clocking & PLLs
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter
Mario Mercandelli*1, Alessio Santiccioli*1, Simone Mattia Dartizio*1,
Francesco Buccoleri1, Luca Avallone2, Angelo Parisi1, Andrea Leonardo Lacaita1, Michael Peter Kennedy2, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy University College Dublin, Dublin, Ireland f
Abanob Shehata1, Francesco Tesolin1, Saleh Karman1, Luca Bertulessi1,
ISSCC 2021 Session 32 Clocking & PLLs
A 14nm Analog Sampling Fractional-N PLL with a Digital-toTime Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels
Wanghua Wu1, Chih-Wei Yao1, Chengkai Guo1, Pei-Yuan Chiang1,
requires sub-100fs rms jitter to support 64-QAM and 2×2 MIMO under non-ideal channel conditions [1]. Although fractional-N phaselocked loops (PLLs) employing digital-to-time converters (DTCs) and sampling phase detectors
Pak-Kim Lau1, Lei Chen1, Sang Won Son1, Thomas Byunghak Cho2 Samsung S
ISSCC 2021 Session 32 Clocking & PLLs
A 365fsrms-Jitter and −63dBc-Fractional Spur 5.3GHz-RingDCO-Based Fractional-N DPLL Using a DTC Second/ThirdOrder Nonlinearity Cancelation and a Probability-DensityShaping ΔΣM
Hangi Park*1, Chanwoong Hwang*1, Taeho Seong*1,2, Yongsun Lee3, Jaehyouk Choi1
data-rates by combining more carrier components, 5G RF transceivers require many carrier frequencies, resulting in the situation of many LC PLLs occupying a large silicon area. Ring-oscillator-based digital PLLs (RO-DPLL
KAIST, Daejeon, Korea Ulsan National Institute of Science and Technolo
ISSCC 2020 Session 17 Clocking & PLLs
A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz
3rd-Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA
Chao Fan , Jun Yin , Chee-Cheow Lim , Pui-In Mak , Rui P. Martins 1 1 1 1 1,2 University of Macau, Macau, China University of Lisboa, Lisbon, Portugal 1 2 Low-power mm-wave sensors using an FMCW radar technology are open