A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique

📋 论文概要

本文提出了一种采用非线性复制技术的分数-N采样锁相环（SPLL），有效抑制了数字时间转换器（DTC）非线性引起的分数杂散和带内相位噪声恶化，实现了76fsrms的极低抖动和-65dBc的分数杂散性能。该技术通过复制DTC的非线性特性并加以补偿，解决了传统DTC方案中非线性限制SPLL在分数-N模式下性能的关键问题。

💡 主要创新点

• 提出非线性复制技术（Nonlinearity-Replication Technique），通过复制并补偿DTC的非线性，显著降低分数杂散和带内相位噪声。

🏷 关键词

📄 原文摘要

most popular architecture for generating ultralow-jitter signals due to their high-gain sampling phase detectors (SPDs) that can significantly reduce in-band phase noise (PN). However, to maintain this advantage even in the fractional-N mode, SPLLs must remove the quantization error (Q-error) of the ΔΣM very precisely. The use of a digital-to-time converter (DTC) before the SPD [1] (top left of Fig. 10.5.1) is a common solution, but the inherent non-linearity (NL) of the DTC, i.e., NLDTC, introduces fractional spurs and the leakage of the Q-error, which increases the inband PN. There are two approaches that are used widely to reduce NLDTC. The first approach (①) is to use a typical DTC and then compensate for NLDTC using a digital predistortion (DPD) that modifies the accumulated ΔΣM code, i.e., DAQ, to have

👥 作者与机构

Yuhwan Shin*1,2, Junseok Lee*1,2, Juyeop Kim*1,2, Yongwoo Jo1,2, Jaehyouk Choi2

Korea Advanced Institute of Science and Technology, Daejeon, Korea Seoul National University, Seoul, Korea *Equally Credited Authors (ECAs) 1 2 Sampling PLLs (SPLLs) are currently the