2024

Semiconductor Industry: Present & Future Kevin Zhang Senior Vice President of Business Development & Overseas Operations Office

Racing Down the Slopes of Moore’s Law Bram Nauta

Computing in the Era of Generative AI Jonah Alben AI Will Transform Your Business An important takeaway from how DLSS reshaped NVIDIA’s core business is that AI should not be viewed solely as a revenue opportunity. Instead, believe that it will fundamentally transform the semiconductor industry – and your business.

Fueling Semiconductor Innovation and Entrepreneurship in the Next Decade Lip-Bu Tan

An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM

A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter

A 45.5fs-Integrated-Random-Jitter and -75dBc-IntegerBoundary-Spur BiCMOS Fractional-N PLL with Suppression

A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique

A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion

An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051%

AMD InstinctTM MI300 Series Modular Chiplet Package – HPC and AI Accelerator for Exa-Class Systems

A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint The 3D clock forwarding methodology enables extension of the SMEM from 16 to 32MB without expanding the original area footprint (4.6MB/mm2). The SMEM access energy is measured for both top die and bottom die banks to be 1.84 and 1.99pJ/B, respectively, at nominal frequency of 500MHz (Fig. 11.2.3) with 0.15pJ/B attributed to the inter-die access. From post-layout RC extracted simulations, only 0.03pJ/B of the access energy is attributed to the 3D interconnects. While on-die temperatures may be a concern for

Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge

IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip

Monolithically Integrated Sub-63 fJ/b 8-Channel 256Gb/s Optical Transmitter with Autonomous Wavelength Locking in 45nm CMOS SOI

A mm-Wave/Sub-THz Synthesizer-Free Coherent Receiver with Phase Reconstruction Through Mixed-Signal Kramer-Kronig Processing

A Scalable and Instantaneously Wideband 5GS/s RF Correlator Based on Charge Thresholding Achieving 8-bit ENOB and 152 TOPS/W Compute Efficiency

A 19μW 200Mb/s IoT Tag Demonstrating High-Definition Video Streaming via a Digital-Switch-Based Reconfigurable 16-QAM Backscatter Communication Technique

A Packageless Anti-Tampering Tag Utilizing Unclonable Sub-THz Wave Scattering at the Chip-Item Interface

A 64.4% Efficiency 5.8GHz RF Wireless Power Transfer Receiver with GaAs E-pHEMT Rectifier and 45.2μs MPPT Time SIDITO Buck-Boost Converter Using VOC Prediction Scheme

A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry

A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets

A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process Figure 13.2.4(a) shows a conceptual DRAM read block diagram. The DLL matches the skew of CLK and DQS. The quadrature-error corrector (QEC) matches the 4-phase skew.

A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization

A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS

A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration lines can be reduced by ¼ compared to a conventional direct feedback DFE [1]. Furthermore, instead of using a CML buffer in the current-summing DFE, the CTLE serves as the DFE summer; hence, overall power consumption is reduced.

A 1Tb Density 3b/Cell 3D-NAND Flash on a 2YY-Tier Technology with a 300MB/s Write Throughput

A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with

A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency

A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC

A/mm2 Scalable Distributed All-Digital 6×6 Dot-LDOs Featuring Freely Linkable Current-Sharing Network: A Fine-Grained On-Chip Power Delivery Solution in 28nm CMOS

Proactive Voltage Droop Mitigation Using Dual-ProportionalDerivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS

A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion

A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU

A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator

A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET

A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS the delay of the DTC based on the LMS calibration method. To satisfy timing constraints, the critical digital blocks are designed with customized logic circuits using low-threshold transistors. The whole HPLL can operate at the minimum voltage of 0.45V (D/VCO at 0.4V) without requiring any voltage booster or bias current.

KASP: A 96.8% 10-Keyword Accuracy and 1.68µJ/Classification Keyword Spotting and Speaker Verification Processor Using Adaptive Beamforming and Progressive Wake-Up

A Monolithic 10.5W/mm2 600MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS

A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch the activated cell data are modified by the driver via BL and BLB. To weaken the force of the cell, the supply voltage for the bit cell is isolated from VDD by a PMOS header. In the second cycle, the write driver loads the 0s and the other rows are activated.

A 2048×60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia

A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture

Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node

LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations

e-Chimera: A Scalable SRAM-Based Ising Macro with Enhanced-Chimera Topology for Solving Combinatorial Optimization Problems Within Memory

A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2

A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs

A 2.7-to-13.3μJ/boot/slot Flexible RNS-CKKS Processor in 28nm CMOS Technology for FHE-Based Privacy-Preserving Computing

A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems