A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm

📋 论文概要

本文提出了一种采用动态偏置环放大器的12位400MS/s流水线-逐次逼近型ADC，解决了传统环放大器最后一级偏置受失配和PVT变化影响的问题，实现了2.08mW功耗和64.4dB SNDR。

💡 主要创新点

• 提出了一种对失配和PVT变化具有容忍性的动态偏置环放大器，替代传统电阻偏置方式。
• 基于该环放大器设计了低功耗高性能的流水线-逐次逼近型ADC架构，在400MS/s下达到12位精度。
• 创新性地融合了动态偏置技术与流水线-逐次逼近型结构，在低功耗下实现高线性度。

🏷 关键词

📄 原文摘要

energy-efficient alternatives to OTAs for switchedcapacitor residue amplifiers. A ring amplifier is essentially a cascaded multi-stage inverter-based amplifier that is stabilized by a dominant pole at the last stage output with sub-threshold biasing. Although ring amplifiers offer slew-based charging, wide output swing, and high gain, the last stage biasing is still problematic considering mismatch and PVT variation. The self-biased ring amplifier [1] (Fig. 9.2.1 (a)) biases the last stage with a resistor placed in the 2nd-stage. While this IR-drop-based biasing effectively tracks first-order PVT variation and demonstrates a reasonable tolerance to VT variation [2], covering a wide range of variations with a fixed resistance is challenging due to the nonlinear relationship between (VGS - VTH) and IDS. The fixed resistor is replaced with a

👥 作者与机构

Yong Lim*, Jaehoon Lee*, Jongmi Lee, Kwangmin Lim, Seunghyun Oh,

Jongwoo Lee, Sung-Ung Kwak Samsung Electronics, Hwaseong, Korea *Equally Credited Authors (ECAs) Ring amplifiers [1-9] are promising