A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/TimeDomain ADC with Common-Mode Input Tracking

📋 论文概要

提出了一种76mW 40GS/s 7位时间交织混合电压/时间域ADC，通过共模输入跟踪技术降低校准复杂度并提高能效，适用于50+Gb/s链路中的DSP均衡和PAM-4调制。

💡 主要创新点

• 采用混合电压/时间域架构，结合电压域SAR和时间域转换的优势，提升子ADC速度并降低输入电容负载。
• 引入共模输入跟踪技术，简化时间交织ADC的校准需求，降低功耗和面积开销。

🏷 关键词

📄 原文摘要

Hillsboro, OR 1 2 Fast, low-power ADCs with ~5-6 effective bits of resolution are a key element of 50+Gb/s links, which often use DSP-based equalization to compensate for high channel loss and high-order modulation schemes (e.g. PAM-4) to push link speed. Voltage-domain SAR ADCs are commonly time-interleaved (TI) to reach these speeds [1-2] but often require calibration-intensive techniques such as multi-comparator loop-unrolling [2] or pipelining to increase sub-ADC speed beyond ~1GS/s, which is critical to reduce area and improve bandwidth by lowering capacitive input load. Time-domain ADCs can offer a fast (>3GS/s), energy efficient [3] alternative well-suited to deeply scaled CMOS implementation. However, reliance on matched gate delays instead of capacitive weights

👥 作者与机构

Amy Whitcombe1, Somnath Kundu2,4, Hariprasad Chandrakumar2,

Abhishek Agrawal2, Thomas Brown2, Steven Callender3, Brent Carlton2, Stefano Pellerano2 Intel, Santa Clara, CA Intel, Hillsboro, OR 3 Intel, Fort Collins, CO 4 now with AMD,