A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm2 Current-Density FoM

📋 论文概要

该论文提出了一种并联开关电容混合降压转换器，通过电压转换比感知拓扑优化器来优化拓扑结构，旨在解决紧凑电感下DCR升高导致的效率下降问题。实现了94.1%的峰值效率和4.2A/mm²的电流密度。

💡 主要创新点

• 提出了一种电压转换比感知的拓扑优化器，能够自动搜索最优的并联开关电容混合降压拓扑。
• 通过并联开关电容路径分担部分功率传输，显著降低了电感电流，从而允许使用更小体积的电感并提升功率密度。

🏷 关键词

📄 原文摘要

pervasive trend across multiple markets, including the sector for buck DC-DC converters. One of the cardinal challenges in achieving optimized power density is navigating the intrinsic trade-off between an inductor’s volume and its parasitic DC resistance (DCR); miniaturizing the inductor invariably leads to elevated DCR. To enhance efficiency even when using compact inductors, many hybrid buck converter topologies have been investigated [1–4]. These hybrid inductor-capacitor innovations aim to mitigate inductor current (IL) by means of additional capacitive power delivery. A straightforward method for designing hybrid converters involves substituting one switch in a switched-capacitor (SC) converter with an inductor. As illustrated in the upper-left of Fig. 28.5.1, employing

👥 作者与机构

Hyunki Han, Jeong-Hyun Cho, Woojin Jang, Yousung Park, Jiho Lee, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology, Daejeon, Korea Increasing power density—delivering more power in a smaller footprint—stands as a