A Synthesizable Design-Agnostic Timing Fault Injection Monitor Covering 2MHz to 1.26GHz Clocks in 65nm CMOS

📋 论文概要

本文提出了一种可综合、设计无关的时序故障注入监测器，覆盖2MHz至1.26GHz的宽时钟频率范围，用于检测由时钟信号或电压篡改等低成本手段引起的故障注入攻击，保障芯片安全。

💡 主要创新点

• 提出了一种设计无关的监测架构，无需修改原电路设计即可集成，降低了使用门槛。
• 实现了超宽频率范围（2MHz-1.26GHz）的时序故障检测，涵盖大多数数字电路工作频率。
• 采用标准单元可综合设计，便于在65nm CMOS工艺中实现低开销、高兼容性的安全监测。

🏷 关键词

📄 原文摘要

Fault Injection Attacks (FIAs) are powerful attacks that induce and exploit faults in chips to create severe security consequences like faulty results, OS security bypass, and information leakage [1-3]. This paper focuses on low-cost FIAs that induce erroneous outputs by tampering with the clock signals and/or supply voltages via software and hardware exploits and/or physical interference (EM coupling, temperature, etc.). FIAs that directly flip bits through high-energy lasers, particles, or other advanced and costly means are out of our scope, but solutions on compact and standard-cell compatible detectors can be readily combined to complement our defense (like in [4]). We categorize FIA-induced clock glitches into 12 basic types (Fig. 16.5.1), where T1-T2 and T5-T12 aim at inducing error via timing violation, while T3-T4 induce errors by skipping the clock cycles of a partial computation block. These 12 types of glitch patterns form the basis

👥 作者与机构

Yan He, Kaiyuan Yang

Rice University, Houston, TX