技术领域

Digital Processors

268 篇相关论文 (2008–2026)

ISSCC 2026 Session 2 Digital Processors
A 0.24mJ/Frame Quadratic Interpolation 4DGS Processor with Recursive Computation Reuse and Tree-Based Parallel-Rendering
Xiaolong Yang, Yang Wang, Wende Xu, Yubin Qin, Huanyu Wang, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu,
Abstract 4D Gaussian Splatting (4DGS) has widespread applications in fields such as VR, AR and industrial simulation. However, 4DGS suffers from significant memory requirements, redundant computations and low PE utilizat
Tsinghua University, Beijing, China
ISSCC 2026 Session 2 Digital Processors
Spyre: An Inference-Optimized Scalable AI Accelerator for Enterprise Workloads
Matthew Cohen1, Monodeep Kar1, Swagath Venkataramani1, Viji Srinivasan1, Brian Veraa2, Matthew Ziegler1, Nianzheng Cao1,
Michael Guillorn1, Sandra Woodward3, JohnDavid Lancaster1, Josh Hursey4, Kyu-hyoun Kim1, Alberto Mannari5, Amrit Nagarajan1, Ananda Samajdar1, Bahman Hekmatshoartabari1, Bob Galbraith3, Ching Zhou1, Dave Satterfield1, Gr
ISSCC 2026 Session 2 Digital Processors
A 71.3mJ/Frame End-to-End Driving Processor with Flexible Heterogeneous Core Orchestration via Sparsity Reasoning
Jueun Jung*1,2, Sangho Lee*1, Junghyun Yoo2, Ghangmin Yun2, Kyuho Jason Lee2
*Equally Credited Authors (ECAs) 1 Abstract A multi-modal end-to-end driving processor is proposed with 4 features: 1) a sparsity reasoning unit to maximize sparsity exploitation, 2) a flexible sparse-dense heterogeneous
Ulsan National Institute of Science and Technology, Ulsan, Korea, 2Yon
ISSCC 2026 Session 2 Digital Processors
A Quad-Chiplet AI SoC with Full-Chip Scalable Mesh Over 16Gb/s UCIe-Advanced Die-to-Die Interface for Large-Scale AI Inferencing
Chang-Hyo Yu, Jaewan Bae, Jinseok Kim, Hongyun Kim, Wongyu Shin, Jae-Sung Yoon, Young-Jae Jin, Jungju Oh, Jaebong Lee, E
Sungpill Choi, Donghan Kim, Hyunje Jo, Hyunho Kim, Hyungseok Heo, Hyunsung Kim, Seung-Goo Kim, Myunghoon Choi, Sangeun Je, Junhee Ham, Juyeong Yoon, Yashael Faith Arthanto, Sung-il Bae, Sanggyu Park, Joungwoo Lee, Heeyou
ISSCC 2026 Session 2 Digital Processors
A 1286fps 0.39mJ/Frame Modeling/Rendering Unified 3D GS Processor with Locality-Optimized Computation and Reconfigurable Architecture
Hedi Wang*, Xiaoyu Feng*, Weichen Gao, Huazhong Yang, Yongpan Liu
*Equally Credited Authors (ECAs) Abstract A modeling/rendering unified 3D GS processor is proposed with: 1) A locality-aware dynamic fine-grained rendering engine for reduced redundant computation. 2) A locality-optimize
Tsinghua University, Beijing, China
ISSCC 2026 Session 2 Digital Processors
AMD Instinct MI350 Series GPUs: CDNA 4-Based 3D-Stacked 3nm XCDs and 6nm IODs for AI applications
Ramasamy Adaikkalavan1, Alan Smith1, Teja Singh1, Sundar Rangarajan1, Eric Chapman1, Samuel Naffziger2, Subramaniam Maiy
Sriram Sundaram1, Mark Silla1, Duncan Law5, Kathy Hoover1, Samuel Lipson1, Kevin Duda2, Vinay Parthasarathy6, Deepesh John1, Hanish Vemulapalli1, Srinivas Pavan Kumar Gade7 AMD, Austin, TX, 2AMD, Fort Collins, CO, 3AMD,
ISSCC 2025 Session 2 Digital Processors
STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming
Kai-Ping Lin1, Tong Wu1, Chang-Pao Lin1, Po-Wei Chen1, Zhi-Jun Zhang1,
driving ultra-high-definition (UHD) TVs and screens, offering users an immersive experience. However, the scarcity of 8K-UHD streams and the high cost of transmission bandwidth necessitate the use of ISP techniques on te
Win-San Khwa2, Meng-Fan Chang2, Chao-Tsung Huang1 National Tsing Hua U
ISSCC 2025 Session 2 Digital Processors
A 210fps Image Signal Processor for 4K Ultra HD True Video Super Resolution
Ying-Sheng Lin1, Jun Nishimura2, Chia-Hsiang Yang1
Google, Mountain View, CA 1 2 Video super-resolution (VSR) aims to convert low-resolution (LR) videos to high-resolution (HR) videos with high image quality [1]. It can be used for various video applications, such as str
National Taiwan University, Taipei, Taiwan
ISSCC 2025 Session 2 Digital Processors
IRIS: A 8.55mJ/frame Spatial Computing SoC for Interactable Rendering and Surface-Aware Modeling with 3D Gaussian Splatting
Seokchan Song, Seryeong Kim, Wonhoon Park, Jongjun Park, Sanghyuk An,
applications, which demand a real-time and user-interactive 3D graphics system [1-3]. This requires real-time surface-aware modeling (SAM) to transfer a physical object to the virtual world, and interactive photorealisti
Gwangtae Park, Minseo Kim, Hoi-Jun Yoo KAIST, Daejeon, Korea Interacti
ISSCC 2025 Session 2 Digital Processors
mJ/Frame 373fps 3D GS Processor Based on Shape-Aware Hybrid Architecture Using Earlier Computation Skipping and Gaussian Cache Scheduler
Xiaoyu Feng*, Hedi Wang*, Chen Tang, Tongda Wu, Huazhong Yang, Yongpan Liu
applications like virtual reality and embodied AI. Unlike traditional Neural Radiance Fields (NeRF) [1], the novel 3D Gaussian Splatting approach (3D GS) [2] circumvents NeRF’s frequent sampling and intensive network inf
Tsinghua University, Beijing, China *Equally Credited Authors (ECAs) 3
ISSCC 2025 Session 2 Digital Processors
IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator
Gerald Strevig1, Chris Berry2, Rahul Rao3, Noam Jungmann4, Michael Sperling2,
Michael Becht2, Eduard Herkel5, Matthias Pflanz5, Pat Meaney2, Michael Romain2, Mark Cichanowski1, Amanda Venton1, David Wolpert2, Elazar Kachir4, Luke Hopkins2, Tim Bubb2, Andreas Arp5, Daniel Kiss5, Simon Büchsenstein5
ISSCC 2025 Session 2 Digital Processors
A 0.52mJ/Frame 107fps Super-Resolution Processor Exploiting Pseudo-FP6 Sparsity for Mobile Applications
Xuyang Duan, Xinhua Shi, Zikang Zhou, Zhiyi Shu, Yitong Rong, Yufan Chen,
increasingly employed across various domains. The ability to recover fine details is especially critical in mobile applications such as gaming, video, and photography [1]. However, mobile devices are usually sensitive to
Zhen Yang, Menghan Li, Jun Han Fudan University, Shanghai, China Super
ISSCC 2025 Session 2 Digital Processors
“Zen 5”: The AMD High-Performance 4nm x86-64 Microprocessor Core
Teja Singh1, Spence Oliver1, Sundar Rangarajan1, Shane Southard1,
Carson Henrion2, Alex Schaefer1, Brett Johnson2, Sarah Bartaszewicz Tower1, Kathy Hoover1, Deepesh John1, Ted Antoniadis1, Shravan Lakshman1, Vibhor Mittal1, Brian Kasprzyk1, Ross McCoy1, Kurt Mohlman1, Anitha Mohan1, Ho
ISSCC 2025 Session 16 Digital Processors
SambaNova SN40L: A 5nm 2.5D Dataflow Accelerator with Three Memory Tiers for Trillion Parameter AI
Raghu Prabhakar, Junwei Zhou, Darshan Gandhi, Youngmoon Choi,
Mahmood Khayatzadeh, Kyunglok Kim, Uma Durairajan, Jeongha Park, Satyajit Sarkar, Jinuk Luke Shin SambaNova Systems, Palo Alto, CA The SN40L is the latest-generation Reconfigurable Dataflow Unit (RDU) from SambaNova Syst
ISSCC 2025 Session 16 Digital Processors
Tomahawk5: 51.2Tb/s 5nm Monolithic Switch Chip for AI/ML Networking
Asad Khamisy1, Mohan Kalkunte1, Peter Del Vecchio1, Yokai Cheok1, Greg Barsky1,
(BCM78900 series, aka TH5) chip and the challenges of implementing a 51.2Tb/s advanced Ethernet switch in a monolithic die. We will describe several technologies that enabled TH5 realization and its advanced capabilities
Karlheinz Muth1, Reza Sharifi2 Broadcom, San Jose, CA Broadcom, Irvine
ISSCC 2024 Session 2 Digital Processors
BayesBB: A 9.6Gbps 1.61ms Configurable All-MessagePassing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm CMOS
Yi Zhang*1,2, Wenyue Zhou*1,2, Yiwei Zhang1,2, Houren Ji1,2, Yongming Huang1,2,
7.4 illustrates the implementation details of the MIMO-BP detector, utilizing a fully unfolded architecture with 5 iterations. The Gaussian approximation of interference is first measured to support the posterior message
Xiaohu You1,2, Chuan Zhang1,2 Southeast University, Nanjing, China Pur
ISSCC 2024 Session 2 Digital Processors
A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems unit computes the soft information by piece-wise linear functions. The channel memory bank includes one channel-sample memory and one channel-difference memory for storing the encoded Gram matrix coefficients.
Tang Lee, Ting-Yang Chen, I-Hsuan Liu, Chia-Hsiang Yang, Figure 2.6.4 shows the detailed architecture and optimization t
The mean values are computed along the diagonal band of the submatrix in a block-byblock manner. It is noted that the mean values for the lower-left and upper-right blocks can be derived from the symbols updated in the p
ISSCC 2024 Session 2 Digital Processors
A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices
Shiyu Guo1, Sachin Sapatnekar2, Jie Gu1
University of Minnesota, Minneapolis, MN includes a sub-group of user-defined objects inside. After the BBOX Intersection Evaluator (BBIE) detects intersection with TBBOX, the Triangle Mesh Intersection Evaluator (TIE) co
Northwestern University, Evanston, IL
ISSCC 2024 Session 2 Digital Processors
ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications
Chang-Hyo Yu, Hyo-Eun Kim, Sungho Shin, Kyeongryeol Bong, Hyunsuk Kim,
Yoonho Boo, Jaewan Bae, Minjae Kwon, Karim Charfi, Jinseok Kim, Hongyun Kim, Myeongbo Shim, Changsoo Ha, Wongyu Shin, Jae-Sung Yoon, Miock Chi, Byungjae Lee, Sungpill Choi, Donghan Kim, Jeongseok Woo, Seokju Yoon, Hyunje
ISSCC 2024 Session 2 Digital Processors
Emerald Rapids: 5th-Generation Intel® Xeon® Scalable Processors
Ashley O. Munch1, Nevine Nassif1, Carleton L. Molnar1, Jason Crop2,
Rich Gammack1, Chinmay P. Joshi3, Goran Zelic1, Kambiz Munshi1, Min Huang4, Charles R. Morganti2, Sireesha Kandula1, Arijit Biswas1 Intel, Hudson, MA 2 Intel, Fort Collins, CO 3 Intel, Hillsboro, OR 4 Intel, Santa Clara,
ISSCC 2024 Session 2 Digital Processors
“Zen 4c”: The AMD 5nm Area-Optimized x86-64 Microprocessor Core
These area optimizations resulted in a “Zen 4c” core, including the L2 cache, that was, 35% smaller than the “Zen 4” cor
3.84mm2. Side-by-side images shown in Fig. 2.2.3. To fit two CCXs onto one chiplet die, the L3 cache in one CCX was reduced from 32MB to 16MB. The extra frequency margin also allowed pairs of L3 data macros to be combined
ISSCC 2024 Session 2 Digital Processors
A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC
Anshul Varma1, Sumanth Gururajarao1, HsinChen Chen1, Tao Chen1,
Gordon Gammie1, Hugh Mair2, Jen-Hang Yang3, Hao-Hsiang Yu3, Shun-Chieh Chang3, Cheng-Hao Yang3, Li-An Huang3, Kumar Ramanathan1, Ramesh Halli4, Efron Ho1, Ta-Wen Hung3, Sung S.-Y. Hsueh3, LiangChe Li3, Achuta Thippana1,
ISSCC 2024 Session 16 Digital Processors
A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm
Jieun Park, Yong Ki Lee, Karpinskyy Bohdan, Yunhyeok Choi, Jonghoon Shin,
cryptographic algorithms, employing random numbers in a variety of cryptographic applications pursuing data integrity, confidentiality, and authenticity. They often require high-throughput capabilities for scenarios such
Hyo-Gyuem Rhew, Jongshin Shin Samsung Electronics, Hwaseong, Korea Tru
ISSCC 2024 Session 16 Digital Processors
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-LocallyAsynchronous Operation Based on Tunable Replica Circuits random delay causes the availability of SMA outputs to downstream operations to be further temporally scattered within CLK boundary. The full 128b SMA output is never latched together due to all four TRCs being forced to have different random delays, recomputed every clock cycle.
Sirish Oruganti*1, Meizhi Wang*1, Vishnuvardhan V. Iyer1, Yipeng Wang1,
Mengtian Yang1, Raghavan Kumar2, Sanu K. Mathew2, Jaydeep P. Kulkarni1 While power and coarse-grained EM SCA target aggregated signatures, fine-grained EM SCA scans the chip and attacks specific activity regions. Combating
ISSCC 2024 Session 16 Digital Processors
PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-Channel Chip-to-Chip Interface in 28nm CMOS
Mao Li1, Zhaoqing Wang1, Sanu K. Mathew2, Vivek De2, Mingoo Seok1
Intel, Hillsboro, OR 1 2 A probing attack on PCB signal traces poses a substantial threat, as it provides an avenue for eavesdropping on transmitted data between chips. This technique can even be exploited for a complete
Columbia University, New York, NY
ISSCC 2024 Session 16 Digital Processors
A Synthesizable Design-Agnostic Timing Fault Injection Monitor Covering 2MHz to 1.26GHz Clocks in 65nm CMOS
Yan He, Kaiyuan Yang
Fault Injection Attacks (FIAs) are powerful attacks that induce and exploit faults in chips to create severe security consequences like faulty results, OS security bypass, and information leakage [1-3]. This paper focuse
Rice University, Houston, TX
ISSCC 2024 Session 16 Digital Processors
High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking
Sudhir Shrikantha Kudva1, Mahmut Ersin Sinangil1, Stephen Tell2,
Nikola Nedovic1, Sanquan Song1, Brian Zimmer1, C. Thomas Gray2 Nvidia, Santa Clara, CA Nvidia, Durham, NC 1 2 causes each inverter to have a slightly different VTC and the following stages are used to amplify the voltage
ISSCC 2024 Session 16 Digital Processors
3nm Physical Unclonable Function with Multi-Mode Self-Destruction and 3.48×10-5 Bit Error Rate
Eric Hunt-Schroeder1, Parker Lin-Butler2, Amit Degada1, Tian Xia2
generate secure encryption keys by exploiting random and unpredictable variations in the manufacturing process. However, achieving an acceptably low Bit Error Rate (BER) below 1×10-4 remains a big challenge. Stable bit i
Marvell, Burlington, VT University of Vermont, Burlington, VT 1 2 Sili
ISSCC 2024 Session 16 Digital Processors
A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems
Yihong Zhu1,2, Wenping Zhu1,2, Yi Ouyang1, Junwen Sun1,2, Min Zhu3, Qi Zhao1,2,
Jinjiang Yang1, Chen Chen1,2, Qichao Tao1,2, Guang Yang1,2, Aoyang Zhang1, Shaojun Wei1,2, Leibo Liu1,2 Tsinghua University, Beijing, China Beijing National Research Center for lnformation Science and Technology (BNRist)
ISSCC 2024 Session 16 Digital Processors
A 2.7-to-13.3μJ/boot/slot Flexible RNS-CKKS Processor in 28nm CMOS Technology for FHE-Based Privacy-Preserving Computing
Hyunhoon Lee*, Hyeokjun Kwon*, Youngjoo Lee
*Equally Credited Authors Fully homomorphic encryption (FHE) has been gaining significant attention as a privacypreserving solution for emerging server systems with critical information, which allows the server to perform
Pohang University of Science and Technology, Pohang, Korea
ISSCC 2023 Session 2 Digital Processors
MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural Engines for Metaverse on Mobile Devices
Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
A neural radiance field (NeRF) [1] uses a deep neural network (DNN) to create 3D models by training the DNN to memorize 3D scene geometry from a few photos. Prior work uses conventional computer graphic algorithms, such
Korea Advanced Institute of Science and Technology, Daejeon, Korea
ISSCC 2023 Session 2 Digital Processors
A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots
I-Ting Lin1, Zih-Sing Fu1, Wen-Ching Chen2, Liang-Yi Lin2, Nian-Shyang Chang2,
(AMRs) have proven useful for smart factories and have potential to revolutionize critical missions, such as disaster rescue [1]. As illustrated in Fig. 2.5.1, AMRs can perceive the environment, plan for assigned tasks a
Chun-Pin Lin2, Chi-Shi Chen2, Chia-Hsiang Yang1 National Taiwan Univer
ISSCC 2023 Session 2 Digital Processors
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing
Yen-Lung Chen*1, Chung-Hsuan Yang*1, Yi-Chung Wu*1, Chao-Hsi Lee2,
Wen-Ching Chen3, Liang-Yi Lin3, Nian-Shyang Chang3, Chun-Pin Lin3, Chi-Shi Chen3, Jui-Hung Hung2,4, Chia-Hsiang Yang1,2 National Taiwan University, Taipei, Taiwan GeneASIC Technologies, Hsinchu, Taiwan 3 Taiwan Semicondu
ISSCC 2023 Session 2 Digital Processors
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension
Kazushi Kawamura*1, Jaehoon Yu*1, Daiki Okonogi1, Satoru Jimbo1,
Genta Inoue1, Akira Hyodo1, Ángel López García-Arias1, Kota Ando2, Bruno Hideki Fukushima-Kimura2, Ryota Yasudo3, Thiem Van Chu1, Masato Motomura1 Tokyo Institute of Technology, Yokohama, Japan, 2Hokkaido University, Sap
ISSCC 2023 Session 2 Digital Processors
A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET
Bo-Jr Huang, Alfred Tsai, Lear Hsieh, Kathleen Chang, C.-J. Tsai,
Jia-Ming Chen, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Jack Ciao, Barry Chen, Chuck Chang, Ping Kao, Ericbill Wang, Harry H. Chen, Hugh Mair, Shih-Arn Hwang MediaTek, Hsinchu, Taiwan In recent years, mobile gaming has grown
ISSCC 2023 Session 2 Digital Processors
“Zen 4”: The AMD 5nm 5.7GHz x86-64 Microprocessor Core
Benjamin Munger1, Kathy Wilcox1, Jeshuah Sniderman1, Chuck Tung1,
Brett Johnson2, Russell Schreiber3, Carson Henrion2, Kevin Gillespie1, Tom Burd4, Harry Fair1, David Johnson2, Jonathan White1, Scott McLelland1, Steven Bakke1, Javin Olson1, Ryan McCracken1, Matthew Pickett2, Aaron Hori
ISSCC 2023 Session 16 Digital Processors
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching
Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha,
and area efficiency for deep neural network (DNN) processing [1-3]. As shown in Fig. 16.5.1, despite promising macro-level efficiency and throughput, there remain three main challenges to extending gains to system perfor
Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo Korea Advanced
ISSCC 2023 Session 16 Digital Processors
TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration
Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu,
Recommendation Models (DLRMs) have computational and data-movement requirements beyond those seen in typical NN processing. Such beyond-NN applications typically consist of Sparse Gathering (SpG) and Sparse Algebra (SpA)
Shaojun Wei, Shouyi Yin Tsinghua University, Beijing, China Applicatio
ISSCC 2023 Session 16 Digital Processors
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture
Jinshan Yue1, Chaojie He1, Zi Wang1, Zhaori Cong1, Yifan He2, Mufeng Zhou2,
University, Beijing, China 1 2 Computing-in-memory (CIM) has shown high energy efficiency on low-precision integer multiply-accumulate (MAC) [1-3]. However, implementing floating-point (FP) operations using CIM has not b
Wenyu Sun2, Xueqing Li2, Chunmeng Dou1, Feng Zhang1, Huazhong Yang2, Y
ISSCC 2022 Session 33 Digital Processors
A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display
Li-Qun Weng, Li-De Chen, Hao-Chien Cheng, An-You Zheng, Kai-Ping Lin, Chao-Tsung Huang
provides a fullparallax glasses-free 3D viewing experience. Compared to other autostereoscopic techniques, factored displays provide greater depth of field, larger field of view, and smoother perspective switching withou
National Tsing Hua University, Hsinchu, Taiwan Factored displays [1-4]
ISSCC 2022 Session 33 Digital Processors
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction
Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang
Epilepsy is a common neurodegenerative disease that affects more than 50 million people worldwide. Closed-loop neuromodulation is a promising solution to epileptic seizure control through an implantable device that deliv
National Taiwan University, Taipei, Taiwan
ISSCC 2022 Session 33 Digital Processors
A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication
Ji-Soo Chang, Eunsang Jang, Youngkil Choi, Moonkyu Song, Sanghyo Lee,
Gi-Jin Kang, Junho Kim, Shin-Wuk Kang, Uijong Song, Chang-Yeon Cho, Junseo Lee, Kyungduck Seo, Seongwook Song, Sung Ung Kwak Samsung Electronics, Hwaseong, Korea Biometric authentication is a proven and practical way to
ISSCC 2022 Session 2 Digital Processors
Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core
Thomas Burd1, Wilson Li1, James Pistole1, Srividhya Venkataraman1,
Michael McCabe1, Timothy Johnson1, James Vinh1, Thomas Yiu1, Mark Wasio1, Hon-Hin Wong1, Daryl Lieu1, Jonathan White2, Benjamin Munger2, Joshua Lindner2, Javin Olson2, Steven Bakke2, Jeshuah Sniderman2, Carson Henrion3,
ISSCC 2022 Session 2 Digital Processors
A 16nm 785GMACs/J 784-Core Digital Signal Processor Array
with a Multilayer Switch Box Interconnect, Assembled as a, 2×2 Dielet with 10µm-Pitch Inter-Dielet I/O for Runtime
amount of dark silicon area in power-limited SoCs makes it attractive to consider reconfigurable architectures that could intelligently repurpose dark silicon. FPGAs are more efficient than CPUs, but lack temporal dynami
Multi-Program Reconfiguration Uneeb Rathore*, Sumeet Singh Nagi*, Subr
ISSCC 2022 Session 2 Digital Processors
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC
Ashish Nayak1, HsinChen Chen1, Hugh Mair1, Rolf Lagerquist1, Tao Chen1,
Anand Rajagopalan1, Gordon Gammie1, Ramu Madhavaram1, Madhur Jagota1, CJ Chung1, Jenny Wiedemeier1, Bala Meera1, Chao-Yang Yeh2, Maverick Lin2, Curtis Lin2, Vincent Lin2, Jiun Lin2, YS Chen2, Barry Chen2, Cheng-Yuh Wu2,
ISSCC 2022 Session 2 Digital Processors
POWER10TM: A 16-Core SMT8 Server Processor with 2TB/s Off-Chip Bandwidth in 7nm Technology
Rahul M. Rao1, Christopher Gonzalez2, Eric Fluhr3, Abraham Mathews3,
Andrew Bianchi3, Daniel Dreps3, David Wolpert4, Eric Lai3, Gerald Strevig3, Glen Wiedemeier3, Philipp Salz5, Ryan Kruse3 IBM, Bengaluru, India; 2IBM, Yorktown Heights, NY; 3IBM, Austin, TX IBM, Poughkeepsie, NY; 5IBM, Bo
ISSCC 2022 Session 2 Digital Processors
IBM Telum: A 16-Core 5+ GHz DCM
Ofer Geva , Chris Berry , Robert Sonnelitter , David Wolpert , Adam Collura ,
Thomas Strach2, Di Phan1, Cedric Lichtenau2, Alper Buyuktosunoglu3, Hubert Harrer2, Jeffrey Zitz1, Chad Marquart1, Douglas Malone1, Tobias Webel2, Adam Jatkowski1, John Isakson4, Dina Hamid1, Mark Cichanowski4, Michael R
ISSCC 2022 Session 2 Digital Processors
Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor
Nevine Nassif1, Ashley O. Munch1, Carleton L. Molnar1, Gerald Pasdast2,
Sitaraman V. Iyer2, Zibing Yang1, Oscar Mendoza1, Mark Huddart1, Srikrishnan Venkataraman3, Sireesha Kandula1, Rafi Marom4, Alexandra M. Kern1, Bill Bowhill1, David R. Mulvihill5, Srikanth Nimmagadda3, Varma Kalidindi1,
ISSCC 2022 Session 2 Digital Processors
Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing
Wilfred Gomes1, Altug Koker2, Pat Stover3, Doug Ingerly1, Scott Siers2,
Srikrishnan Venkataraman4, Chris Pelto1, Tejas Shah5, Amreesh Rao2, Frank O’Mahony1, Eric Karl1, Lance Cheney2, Iqbal Rajwani2, Hemant Jain4, Ryan Cortez2, Arun Chandrasekhar4, Basavaraj Kanthi4, Raja Koduri6 Intel, Port
ISSCC 2022 Session 15 Digital Processors
Analog Matrix Processor for Edge AI Real-Time Video Analytics
Laura Fick1, Skylar Skrzyniarz1, Malav Parikh1, Michael B. Henry2, David Fick1
Mythic, Austin, TX Mythic, Redwood City, CA 1 2 One of the!salient!hurdles for wide adoption of!machine learning!(ML)!has been!efficient and high-performance!edge compute.!ML developers!use very large, expensive, and pow