⚡ 本页包含 AI 生成的分析内容，仅供参考
本文介绍了一款面向旗舰智能手机的4nm工艺、3.4GHz三档全乱序ARMv9.2 CPU子系统，用于5G移动SoC。该工作首次公开采用全乱序执行的三档CPU架构，旨在实现高性能与能效的平衡，代表了移动SoC设计的范式转变。
Gordon Gammie1, Hugh Mair2, Jen-Hang Yang3, Hao-Hsiang Yu3, Shun-Chieh Chang3, Cheng-Hao Yang3, Li-An Huang3, Kumar Ramanathan1, Ramesh Halli4, Efron Ho1, Ta-Wen Hung3, Sung S.-Y. Hsueh3, LiangChe Li3, Achuta Thippana1, Ericbill Wang3, SA Hwang3 MediaTek, Austin, TX; 2MediaTek, Dallas, TX MediaTek, Hsinchu, Taiwan; 4MediaTek, Bengaluru, India 1 3 Built for upcoming flagship smartphones, this paper describes a new tri-gear CPU subsystem that represents a paradigm shift in mobile SoCs. While tri-gear CPU subsystems have been published [1][2], this work is the first publication to feature Outof-Order (OoO) CPUs in all three gears of the cluster. Implemented in a 4nm CMOS process, four OoO High Efficiency (HE) cores are complemented by three Balanced Performance (BP) cores, and a single High Performance (HP) core. Critically, full hardware DVFS control is achieved through enhancements to the DVFS control
Anshul Varma1, Sumanth Gururajarao1, HsinChen Chen1, Tao Chen1,