Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-LocallyAsynchronous Operation Based on Tunable Replica Circuits random delay causes the availability of SMA outputs to downstream operations to be further temporally scattered within CLK boundary. The full 128b SMA output is never latched together due to all four TRCs being forced to have different random delays, recomputed every clock cycle.

📋 论文概要

该论文提出了一种抗功耗和电磁侧信道攻击的AES-128核心，采用轮对齐的全局同步局部异步架构。通过使每个子模块在每个轮次中随机执行并行、串行或空操作，同时维持总操作数不变，实现了对细粒度电磁扫描攻击的抵抗。

💡 主要创新点

• 提出轮对齐的全局同步局部异步架构，结合随机化操作模式（并行、串行、空操作）来对抗细粒度电磁侧信道攻击。
• 通过在每个轮次中随机分配子模块的活动类型，同时保持总操作数恒定，有效隐藏了特定模块的活动特征。

🏷 关键词

📄 原文摘要

Mengtian Yang1, Raghavan Kumar2, Sanu K. Mathew2, Jaydeep P. Kulkarni1 While power and coarse-grained EM SCA target aggregated signatures, fine-grained EM SCA scans the chip and attacks specific activity regions. Combating this requires making the activity of specific modules stochastic. This work enables modules to operate with variable activities per round (Fig. 16.7.2(c)). Each SMA block can operate either (i) one SMA operation (parallel), (ii) two SMA operations (serial), or (iii) no SMA operations (silent/null) at each round while maintaining a total of exactly 4 SMA operations across SMAs. Consequently, the correlation between transient EM data captured at specific locations and the key prediction degrades due to the increased entropy in module activity. The TRCs are also designed such that they output a 1 after the TRC delay but a 0 quickly after their input goes 0, which enables serial operation on two data sections by the same

👥 作者与机构

Sirish Oruganti*1, Meizhi Wang*1, Vishnuvardhan V. Iyer1, Yipeng Wang1,