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ISSCC 2024Session 2 · PROCESSORS AND COMMUNICATION SOCSDigital Processors40nm

BayesBB: A 9.6Gbps 1.61ms Configurable All-MessagePassing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm CMOS

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文提出BayesBB,一种支持B5G/6G去蜂窝大规模MIMO的9.6Gbps可配置全消息传递基带加速器。采用40nm工艺实现了1.61ms的低系统延迟,解决了传统基带处理的高延迟和低吞吐量问题。

💡 主要创新点

核心指标
9.6Gbps, 1.61ms
工艺节点
40nm
重要性
发表年份
ISSCC 2024

🏷 关键词

BayesBB全消息传递基带加速器去蜂窝大规模MIMO40nm

📄 原文摘要

7.4 illustrates the implementation details of the MIMO-BP detector, utilizing a fully unfolded architecture with 5 iterations. The Gaussian approximation of interference is first measured to support the posterior message calculation. Then, the posterior messages are buffered and accumulated to compute the symbol prior probability. Finally, bit LLR messages are derived from the symbol prior probability. The detector benefits from a fully unfolded and pipelined architecture, enjoying a detection latency of 1.44ms. The low-latency detector results in a system latency of 1.61ms, which represents a 2.5× reduction compared to the user latency of 5G [1]. 1 2 The global success of 5G wireless exerts a significant impact on human life [1]. For the forthcoming beyond-5G (B5G) and 6G eras [2], there is demand for wireless networks

👥 作者与机构

Yi Zhang*1,2, Wenyue Zhou*1,2, Yiwei Zhang1,2, Houren Ji1,2, Yongming Huang1,2,

Xiaohu You1,2, Chuan Zhang1,2 Southeast University, Nanjing, China Purple Mountain Laboratories, Nanjing, China *Equally Credited Authors (ECA) Figure 2

分类:Digital Processors · 年份:ISSCC 2024