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ISSCC 2024Session 16 · SECURITY: FROM PROCESSORS TO CIRCUITSDigital Processors4nm

A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm

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📋 论文概要

该论文提出了一种基于自定时环(STR)的真随机数发生器(TRNG),在4nm CMOS工艺上实现了60Mb/s的高吞吐量。通过PVT变化容忍设计,确保在各种工艺、电压和温度变化下保持稳定的熵比特质量,解决了高安全性应用中随机数稳定性问题。

💡 主要创新点

核心指标
60Mb/s
工艺节点
4nm
重要性
发表年份
ISSCC 2024

🏷 关键词

真随机数发生器自定时环PVT变化容忍高吞吐量4nm CMOS

📄 原文摘要

cryptographic algorithms, employing random numbers in a variety of cryptographic applications pursuing data integrity, confidentiality, and authenticity. They often require high-throughput capabilities for scenarios such as financial transactions, real-time data processing, and large-scale communications. In addition, keeping the stable quality of randomness in terms of entropy per bit across wide PVT variations is an essential requirement. Otherwise, an attacker can take advantage of it, causing a serious security vulnerability. In this paper, we propose a Self-Timed Ring (STR) based TRNG (STR-TRNG) designed to be tolerant to PVT variations. Ensuring a consistent ratio between forward and backward delays in each STR stage is essential for reliable operation across all PVT

👥 作者与机构

Jieun Park, Yong Ki Lee, Karpinskyy Bohdan, Yunhyeok Choi, Jonghoon Shin,

Hyo-Gyuem Rhew, Jongshin Shin Samsung Electronics, Hwaseong, Korea True Random Number Generators (TRNGs) are essential for security protocols and

分类:Digital Processors · 年份:ISSCC 2024