DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching

📋 论文概要

提出了一种基于eDRAM存内计算的可重构空间加速器DynaPlasia，采用三模式单元实现动态分辨率，解决了固定IMC宏大小导致的重复内存访问和利用率低的问题。

💡 主要创新点

• 提出三模式单元（Triple-Mode Cell），支持动态分辨率调整，适应不同DNN层维度。
• 设计可重构空间加速器架构，通过动态配置宏大小减少重复内存访问和功耗。
• 基于eDRAM的存内计算，提升能效和面积效率。

🏷 关键词

📄 原文摘要

and area efficiency for deep neural network (DNN) processing [1-3]. As shown in Fig. 16.5.1, despite promising macro-level efficiency and throughput, there remain three main challenges to extending gains to system performance with a high integration level. First, most previous works had a fixed configuration and fixed size of IMC macros, and when the size of macro was smaller than the DNN layer’s dimension, repetitive memory accesses were required for IA/OA, consuming >40% of IMC power. In the opposite case, macros experience underutilization. Second, previous eDRAM-based [4-6] IMCs showed even lower cell density than SRAM-based IMCs [1-3], owing to the area needed to realize a large cell capacitor for long retention time. Third, previous IMC processors [1, 2, 5] employed bit

👥 作者与机构

Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha,

Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo Korea Advanced Institute of Science and Technology, Daejeon, Korea In-memory computing (IMC) processors show significant energy