Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing

📋 论文概要

本文介绍了Ponte Vecchio（PVC），一个异构的petaop级3D处理器，由47个功能块组成，跨越五个工艺节点，通过Foveros和EMIB技术连接，实现单芯片操作，旨在支持可扩展的百亿亿次超级计算。

💡 主要创新点

• 采用多块3D堆叠架构，集成47个功能块，实现异构集成和可扩展性。
• 利用Foveros和EMIB先进封装技术，将不同工艺节点的块连接成单一芯片，提升性能和能效。

🏷 关键词

📄 原文摘要

Srikrishnan Venkataraman4, Chris Pelto1, Tejas Shah5, Amreesh Rao2, Frank O’Mahony1, Eric Karl1, Lance Cheney2, Iqbal Rajwani2, Hemant Jain4, Ryan Cortez2, Arun Chandrasekhar4, Basavaraj Kanthi4, Raja Koduri6 Intel, Portland, OR; 2Intel, Folsom, CA; 3Intel, Chandler, AZ; 4Intel, Bengaluru, India Intel, Austin, TX, 6Intel, Santa Clara, CA 1 5 Ponte Vecchio (PVC) is a heterogenous petaop 3D processor comprising 47 functional tiles on five process nodes. The tiles are connected with Foveros [1] and EMIB [2] to operate as a single monolithic implementation enabling a scalable class of Exascale supercomputers. The PVC design contains >100B transistors and is composed of sixteen TSMC N5 compute tiles, and eight Intel 7 memory tiles optimized for random access bandwidth-optimized SRAM tiles (RAMBO) 3D stacked on two Intel 7 Foveros base dies. Eight HBM2E memory tiles and two TSMC N7 SerDes connectivity tiles are connected

👥 作者与机构

Wilfred Gomes1, Altug Koker2, Pat Stover3, Doug Ingerly1, Scott Siers2,