技术领域

Digital Processors

268 篇相关论文 (2008–2026)

ISSCC 2022 Session 15 Digital Processors
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
Kazutoshi Hirose*, Jaehoon Yu*, Kota Ando, Yasuyuki Okoshi,
Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura Tokyo Institute of Technology, Yokohama, Japan *Equally Credited Authors (ECAs) Since the advent of the Lottery Ticket Hypothes
ISSCC 2021 Session 9 Digital Processors
A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain DivisiveEnergy Normalization for an Always-On Keyword Spotting Device
Dewei Wang, Sung Justin Kim, Minhao Yang, Aurel A. Lazar, Mingoo Seok
In mobile and edge devices, always-on keyword spotting (KWS) is an essential function to detect wake-up words. Recent works achieved extremely low power dissipation down to ~500nW [1]. However, most of them adopt noise-d
Columbia University, New York, NY
ISSCC 2021 Session 9 Digital Processors
A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET
Thierry Tambe1, En-Yu Yang1, Glenn G. Ko1, Yuji Chai1, Coleman Hooper1,
Marco Donato2, Paul N. Whatmough1,3, Alexander M. Rush4, David Brooks1, Gu-Yeon Wei1 Harvard University, Cambridge, MA Tufts University, Medford, MA 3 ARM, Boston, MA 4 Cornell University, New York, NY 1 2 Automatic spee
ISSCC 2021 Session 9 Digital Processors
A 184µW Real-Time Hand-Gesture Recognition System with Hybrid Tiny Classifiers for Smart Wearable Devices
Yuncheng Lu1, Van Loi Le2, Tony Tae-Hyoung Kim1
Nations Innovation Technologies, Singapore, Singapore 1 2 Recently, vision-based hand gesture recognition (HGR) has emerged as a natural and flexible human-computer interaction (HCI) approach. Users can control smart dev
Nanyang Technological University, Singapore, Singapore
ISSCC 2021 Session 9 Digital Processors
PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm
Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst
devices, their usage is also criticized due to lack of explainability, inability to include domain knowledge, and a need for large volumes of training data. To overcome this, researchers are increasingly using probabilis
KU Leuven - MICAS, Leuven, Belgium While deep neural networks have bec
ISSCC 2021 Session 4 Digital Processors
An Area and Energy Efficient 0.12nJ/Pixel 8K 30fps AV1 Video Decoder in 5nm CMOS Process
Tae Sung Kim, Seokhyun Lee, Kyungkoo Lee, Sunyoung Shin,
SeungSick Jun, YongMi Lee, Seungyong Lee, Homin Kang, Changhyun Yim, Yohan Lim, Eikyung Moon, Sukhwan Lim, Kyungah Jeong, Inyup Kang Samsung Electronics, Hwaseong, Korea Major content providers such as YouTube and Netfli
ISSCC 2021 Session 4 Digital Processors
A 91mW 90fps Super-Resolution Processor for Full HD Images
Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang
Super resolution is the process of reconstructing a high-resolution (HR) image from a low-resolution (LR) one. Super-resolution technology enables high-resolution video streaming, image zoom-in, and far object recognitio
National Taiwan University, Taipei, Taiwan
ISSCC 2021 Session 4 Digital Processors
A 144Kb Annealing System Composed of 9×16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems
Takashi Takemoto1, Kasho Yamamoto2, Chihiro Yoshimura2, Masato Hayashi2,
Service, Sapporo, Japan 1 2 Substantial progress has been made on a new computer architecture, known as an annealing processor (AP) [1–4]. The AP can effectively solve NP-hard combinatorial optimization problems by provi
Masafumi Tada3, Hiroaki Saito4, Mayumi Mashimo2, Masanao Yamaoka2 Hita
ISSCC 2021 Session 4 Digital Processors
BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health Monitoring
Jiahao Liu, Zhen Zhu, Yong Zhou, Ning Wang, Guanghai Dai, Qingsong Liu,
health monitoring devices automatically detect abnormalities in users’ biomedical signals (e.g. arrhythmia from an ECG signal or a seizure from an EEG signal) through signal classification. Compared to conventional machi
Jianbiao Xiao, Yuxiang Xie, Zirui Zhong, Hongduo Liu, Liang Chang, Jun
ISSCC 2021 Session 4 Digital Processors
A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7µW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
Davide Rossi1, Francesco Conti1, Manuel Eggiman2, Stefan Mach2,
Alfio Di Mauro2, Marco Guermandi1,3, Giuseppe Tagliavini1, Antonio Pullini2,3, Igor Loi3, Jie Chen1,3, Eric Flamand2,3, Luca Benini1,2 University of Bologna, Bologna, Italy ETH Zurich, Zurich, Switzerland 3 Greenwaves Te
ISSCC 2021 Session 4 Digital Processors
An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET
Colin Schmidt*, John Wright*, Zhongkai Wang, Eric Chang, Albert Ou,
such as deep neural networks (DNNs), increasingly rely on dense arithmetic compute patterns that are ill-suited for general-purpose processors, leading to a rise in domain-specific compute accelerators [1]. Many of these
Woorham Bae, Sean Huang, Anita Flynn, Brian Richards, Krste Asanović,
ISSCC 2021 Session 4 Digital Processors
A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem
Hsinchen Chen1, Rolf Lagerquist1, Ashish Nayak1, Hugh Mair1,
Gokulakrishnan Manoharan1, Ericbill Wang2, Gordon Gammie1, Efron Ho1, Anand Rajagopalan1, Lee-Kee Yong1, Ramu Madhavaram1, Madhur Jagota1, Chi-Jui Chung1, Sudhakar Maruthi1, Jenny Wiedemeier1, Tao Chen1, Henry Hsieh2, Da
ISSCC 2021 Session 3 Digital Processors
Kunlun: A 14nm High-Performance AI Processor for Diversified Workloads
Jian Ouyang, Xueliang Du, Yin Ma, Jiaqiang Liu
In order to be able to handle a wide range of AI applications, such as for speech, image, language and autonomous driving, it is necessary that an AI accelerator be flexible enough to handle diversified workloads. Baidu
Baidu, Beijing, China
ISSCC 2021 Session 3 Digital Processors
The A100 Datacenter GPU and Ampere Architecture
Jack Choquette, Edward Lee, Ronny Krashinsky, Vishnu Balan, Brucek Khailany
Nvidia, Santa Clara, CA The diversity of compute-intensive applications in modern cloud data centers has driven the explosion of GPU-accelerated cloud computing. Such applications include AI deep learning training and in
ISSCC 2021 Session 3 Digital Processors
XBOX Series X: A Next-Generation Gaming Console SoC
Paul Paternoster1, Andy Maki2, Andres Hernandez2, Mark Grossman1,
improvement over the prior generation with up to 2× GPU performance, 3× CPU performance, 2.4× GPU performance/W, 1.7× memory bandwidth and 2× IO bandwidth to feed the additional processing capability and features shown i
Michael Lau1, David Sutherland2, Aditya Mathad3 Microsoft, Sunnyvale,
ISSCC 2021 Session 15 Digital Processors
A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization
balancing. In each macro, 16 VGBLs and 8 HGBLs are activated simultaneously. 2 TCs, are divided into tiles. Each tile ha
position of M macros. The CMA reduces memory accesses by 70.32%, on average, in various NNs. Ruiqi Guo1, Zhiheng Yue1, Xin Si2, Te Hu1, Hao Li1, Limei Tang1, Yabing Wang1, Leibo Liu1, Meng-Fan Chang3, Qiang Li2, Shaojun
ISSCC 2021 Session 15 Digital Processors
A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating
Jinshan Yue1,2, Xiaoyu Feng1, Yifan He1, Yuxuan Huang1, Yipeng Wang2,
Zhe Yuan1, Mingtao Zhan1, Jiaxin Liu1, Jian-Wei Su3, Yen-Lin Chung3, Ping-Chun Wu3, Li-Yang Hung3, Meng-Fan Chang3, Nan Sun1, Xueqing Li1, Huazhong Yang1, Yongpan Liu1 Tsinghua University, Beijing, China Pi2star Technolo
ISSCC 2020 Session 21 Digital Processors
A 5.69mm2 0.98nJ/Pixel Image-Processing SoC with 24b High-Dynamic-Range and Multiple Sensor Format Support for Automotive Applications
Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang,
Chang-Hung Tsai, Ying-Jui Chen, TH Wu, Hue-Min Lin, Han-Liang Chou, Abrams Chen, Andy-HB Wang, WC Gu, Wayne Hsieh, Jing-Ying Chang, Shou-Chun Liao, CT Ho, Larry Chu, Sokonisa Wei, CH Wang, Kevin Jou MediaTek, Hsinchu, Ta
ISSCC 2020 Session 21 Digital Processors
A 1.5µJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots
Chieh Chung, Chia-Hsiang Yang
Autonomous micro robots have been deployed for various applications, ranging from unmanned package delivery to smart aerial surveillance. These robots possess intelligence for perception, make decisions based on the coll
National Taiwan University, Taipei, Taiwan
ISSCC 2020 Session 21 Digital Processors
A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing
Yi-Chung Wu*1, Yen-Lung Chen*1, Chung-Hsuan Yang1, Chao-Hsi Lee2,
Chao-Yang Yu3, Nian-Shyang Chang3, Ling-Chien Chen3, Jia-Rong Chang3, Chun-Pin Lin3, Hung-Lieh Chen3, Chi-Shi Chen3, Jui-Hung Hung2, Chia-Hsiang Yang1 National Taiwan University, Taipei, Taiwan National Chiao Tung Univer
ISSCC 2020 Session 2 Digital Processors
IBM z15: A 12-Core 5.2GHz Microprocessor
Christopher Berry1, Brian Bell2, Adam Jatkowski1, Jesse Surprise1,
John Isakson3, Ofer Geva1, Brian Deskin4, Mark Cichanowski3, Dina Hamid1, Chris Cavitt1, Gregory Fredeman1, Anthony Saporito1, Ashutosh Mishra5, Alper Buyuktosunoglu6, Tobias Webel7, Preetham Lobo5, Pradeep Parashurama5,
ISSCC 2020 Session 2 Digital Processors
A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded
Applications with Integrated Safety MCU, 512b Vector
VLIW DSP, Embedded Vision and Imaging Acceleration Rama Venkatasubramanian1, Don Steiss1, Greg Shurtz2, Tim Anderson1, Kai Chirca1, Raghavendra Santhanagopal1, Niraj Nandan1, Anish Reghunath1, Hetul Sanghvi1, Daniel Wu1,
ISSCC 2020 Session 2 Digital Processors
A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC.
Hugh Mair1, Ericbill Wang2, Ashish Nayak1, Rolf Lagerquist1, Loda Chou2,
Gordon Gammie1, Hsinchen Chen1, Lee-Kee Yong1, Manzur Rahman1, Jenny Wiedemeier1, Ramu Madhavaram1, Alex Chiou2, Blundt Li2, Vincent Lin2, Rory Huang2, Michael Yang2, Achuta Thippana1, Osric Su2, SA Huang2 MediaTek, Aust
ISSCC 2020 Session 2 Digital Processors
A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU
Young Duk Kim, Wookyeong Jeong, Lakkyung Jung, Dongsuk Shin,
Jae Geun Song, Jinook Song, Hyeokman Kwon, Jaeyoung Lee, Jaesu Jung, Myungjin Kang, Jaehun Jeong, Yoonjoo Kwon, Nak Hee Seong Samsung Electronics, Hwaseong, Korea Mobile application processors (APs) must be extremely pow
ISSCC 2020 Session 2 Digital Processors
A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm
Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and, 156mW/mm2 @ 82%-Peak-Efficiency DC-DC Converters
which is finally delivered to the chiplet through a micro-bump face-to-face power grid (Fig. 2.3.7). The SCVR input voltage (up to 2.5V) reduces total input current and the required number of power IOs in the package. Ea
ISSCC 2020 Session 2 Digital Processors
AMD Chiplet Architecture for High-Performance Server and Desktop Products
Samuel Naffziger1, Kevin Lepak2, Milam Paraschou1, Mahesh Subramony2
AMD, Austin, TX 1 2 AMD’s “Rome” and “Matisse” are second-generation AMD Infinity Fabric-based SoCs using 3 unique hybrid process technology chiplets to achieve leading performance, performance/$ and performance/W, targe
AMD, Fort Collins, CO
ISSCC 2020 Session 2 Digital Processors
Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core
Teja Singh1, Sundar Rangarajan1, Deepesh John1, Russell Schreiber1,
design, fabricated in an energy-efficient TSMC 7nm FinFET process. Similar to AMD’s prior-generation core, codenamed “Zen” [1], the Core Complex Unit (CCX) with 4 cores in this version (Fig. 2.1.1) is used across a wide
Spence Oliver1, Rajit Seahra2, Alex Schaefer1 AMD, Austin, TX, 2AMD, M
ISSCC 2019 Session 2 Digital Processors
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D
Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura,
Shohei Maeda, Tomonori Yanagita, Takao Koike, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Tadaaki Yamauchi, Hiroyuki Kondo Renesas Electronics, Kodaira, Japan Automotive architecture has been rapidly
ISSCC 2019 Session 2 Digital Processors
A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots
Vinayak Honkote1, Dileep Kurian1, Sriram Muthukumar1, Dibyendu Ghosh1,
Satish Yada1, Kartik Jain1, Bradley Jackson2, Ilya Klotchkov2, Mallikarjuna Rao Nimmagadda1, Shreela Dattawadkar1, Pranjali Deshmukh1, Ankit Gupta1, Jaykant Timbadiya1, Ravi Pali1, Karthik Narayanan1, Saksham Soni1, Sara
ISSCC 2019 Session 2 Digital Processors
An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things
Utsav Banerjee1, Abhishek Pathak2, Anantha P. Chandrakasan1
Indian Institute of Technology Delhi, New Delhi, India 1 2 Modern public key protocols, such as RSA and elliptic curve cryptography (ECC), will be rendered insecure by Shor’s algorithm [1] when large-scale quantum comput
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2019 Session 2 Digital Processors
A 978GOPS/W Flexible Streaming Processor for RealTime Image Processing Applications in 22nm FDSOI stream up to 1024 cycles, buffering up to one line of HD frames without chaining FIFOs together. Unused SRAM blocks are placed in sleep mode for the full execution duration to minimize power consumption.
Sander Smets1, Toon Goedemé1, Anurag Mittal2, Marian Verhelst1, Crucial to streaming fabrics is their ability to map and
of image processing compute kernels found in typical image processing pipelines, as listed in Fig. 2.2.1. Fig. 2.2.3 demonstrates how 3 of these kernels can be mapped on the presented fabric: horizontal and vertical Sobe
ISSCC 2019 Session 2 Digital Processors
Summit and Sierra: Designing AI/HPC Supercomputers
James A. Kahle1, Jaime Moreno2, Dan Dreps3
IBM Research, Yorktown Heights, NY 3 IBM Systems and Technology, Austin, TX 1 2 The Summit and Sierra Supercomputer Systems, deployed in 2018 at the Department of Energy (DOE) National Laboratories, Oak Ridge (ORNL) and
IBM Research, Austin, TX
ISSCC 2018 Session 2 Digital Processors
A cm-Scale Self-Powered Intelligent and Secure IoT Edge Mote Featuring an Ultra-Low-Power SoC in 14nm Tri-Gate CMOS
Tanay Karnik1, Dileep Kurian2, Paolo Aseron1, Richard Dorrance1,
Erkan Alpman1, Angela Nicoara1, Roman Popov1, Leonid Azarenkov1, Mikhail Moiseev1, Li Zhao1, Santosh Ghosh1, Rafael Misoczki1, Ankit Gupta2, Akhila M2, Sriram Muthukumar2, Saurabh Bhandari2, Yada Satish2, Kartik Jain2, R
ISSCC 2018 Session 2 Digital Processors
A 595pW 14pJ/Cycle Microcontroller with Dual-Mode Standard Cells and Self-Startup for Battery-Indifferent Distributed Sensing
Longyang Lin, Saurabh Jain, Massimo Alioto
Battery-indifferent sensor nodes require continuous operation in spite of the intermittently available battery energy, and hence require low peak-power operation to fit the fluctuating power made available by the harvest
National University of Singapore, Singapore, Singapore
ISSCC 2018 Session 2 Digital Processors
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications
Utsav Banerjee, Chiraag Juvekar, Andrew Wright, Arvind, Anantha P. Chandrakasan
Layer Security (DTLS)
Massachusetts Institute of Technology, Cambridge, MA End-to-end securi
ISSCC 2018 Session 2 Digital Processors
"Zeppelin": An SoC for Multichip Architectures
Noah Beck1, Sean White1, Milam Paraschou2, Samuel Naffziger2
AMD, Fort Collins, CO 1 2 Codenamed “Zeppelin”, AMD’s next-generation System-on-a-Chip (SoC) was designed for use in multiple products and packages in multiple markets, including server, mainstream PC desktop, and high-e
AMD, Boxborough, MA
ISSCC 2018 Session 2 Digital Processors
An Energy-Efficient Graphics Processor Featuring
Fine-Grain DVFS with Integrated Voltage Regulators,
Execution-Unit Turbo, and Retentive Sleep in 14nm Tri-Gate CMOS Pascal Meinerzhagen1, Carlos Tokunaga1, Andres Malavasi1, Vaibhav Vaidya1, Ashwin Mendon1, Deepak Mathaikutty1, Jaydeep Kulkarni1, Charles Augustine1, Minki
ISSCC 2018 Session 2 Digital Processors
IBM z14TM: 14nm Microprocessor for the Next-Generation Mainframe
Christopher Berry1, James Warnock2, John Isakson3, John Badar3,
Brian Bell4, Frank Malgioglio1, Guenter Mayer5, Dina Hamid1, Jesse Surprise1, David Wolpert1, Ofer Geva6, Bill Huott1, Leon Sigal2, Sean Carey1, Richard Rizzolo1, Ricardo Nigaglioni3, Mark Cichanowski3, Dureseti Chidamba
ISSCC 2018 Session 2 Digital Processors
SkyLake-SP: A 14nm 28-Core Xeon® Processor
Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer,
Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang Intel, Santa Clara, CA SkyLake-SP (Scalable Performance), code name SKX, is the next generation Xeon® server proce
ISSCC 2018 Session 17 Digital Processors
A Recursive-Memory Brain-State Classifier with 32-Channel Track-and-Zoom Δ2Σ ADCs and Charge-Balanced Programmable Waveform Neurostimulators
Gerard O'Leary1, M. Reza Pazhouhandeh1, Michael Chang1,
David Groppe2, Taufik A. Valiante3, Naveen Verma4, Roman Genov1 University of Toronto, Toronto, Canada Krembil Neuroscience Center, Toronto, Canada 3 Toronto Western Hospital, Toronto, Canada 4 Princeton University, Prin
ISSCC 2018 Session 17 Digital Processors
A 665μW Silicon Photomultiplier-Based NIRS/EEG/EIT Monitoring ASIC for Wearable Functional Brain Imaging
Jiawei Xu1, Mario Konijnenburg1, Budi Lukita1, Shuang Song2,
Hyunsoo Ha1, Roland van Wegberg1, Erfan Sheikhi1, Massimo Mazzillo3, Giorgio Fallica3, Walter De Raedt2, Chris Van Hoof2,4, Nick Van Helleputte2 imec - Holst Centre, Eindhoven, The Netherlands; 2imec, Leuven, Belgium 3 S
ISSCC 2018 Session 17 Digital Processors
A 330μm×90μm Opto-Electronically Integrated Wireless System-on-Chip for Recording of Neural Activities
Sunwoo Lee, Alejandro J. Cortese, Paige Trexel, Elizabeth R. Agger,
Paul L. McEuen, Alyosha C. Molnar Cornell University, Ithaca, NY Recording neural activity in live animals in vivo poses several challenges. Electrical techniques typically require electrodes to be tethered to the outsid
ISSCC 2018 Session 17 Digital Processors
A 200Mb/s Inductively Coupled Wireless Transcranial Transceiver Achieving 5e-11 BER and 1.5pJ/b Transmit Energy Efficiency
Wen Li1, Yida Duan2, Jan M. Rabaey1
Inphi, Santa Clara, CA 1 2 Recent advancements in medical neural science and brain research have enabled the potential of uninterrupted simultaneous recording of thousands of neurons. To minimize the risk of infection to
University of California, Berkeley, CA
ISSCC 2018 Session 17 Digital Processors
50nW 5kHz-BW Opamp-Less ΔΣ Impedance Analyzer for Brain Neurochemistry Monitoring
Maged El Ansary1, Nima Soltani1, Hossein Kassiri1, Ruben Machado1,
Suzie Dufou1,2, Peter L. Carlen1,2, Michael Thompson1, Roman Genov1 University of Toronto, Toronto, Canada Toronto Western Hospital, Toronto, Canada 1 2 Potassium (K+) and sodium (Na+) ions are the main signal carriers i
ISSCC 2018 Session 17 Digital Processors
A 0.28mΩ-Sensitivity 105dB-Dynamic-Range Electrochemical Impedance Spectroscopy SoC for Electrochemical Gas Detection
Guangyang Qu1, Hanqing Wang1, Yimiao Zhao1, John O'Donnell2,
Colin Lyden3, Yincai Liu1, Junbiao Ding4, Dennis Dempsey2, Leicheng Chen1, Donal Bourke3, Shurong Gu1, Jun Gao1, Lizhu Lu1, Li Wang1, Xuemin Li1, Hongxing Li5, Chao Chu1, Ling Yang1 Analog Devices, Beijing, China; 2Analo
ISSCC 2018 Session 17 Digital Processors
A 0.3V Biofuel-Cell-Powered Glucose/Lactate Biosensing System Employing a 180nW 64dB SNR Passive ΔΣ ADC and a 920MHz Wireless Transmitter
Ali Fazli Yeknami, Xiaoyang Wang, Somayeh Imani, Ali Nikoofard,
Itthipon Jeerapan, Joseph Wang, Patrick P. Mercier University of California, San Diego, La Jolla, CA Wearable physiochemical biosensors offer an exciting opportunity to monitor the concentration of ions and metabolites i
ISSCC 2018 Session 17 Digital Processors
4-Camera VGA-Resolution Capsule Endoscope with 80Mb/s Body-Channel Communication Transceiver and Sub-cm Range Capsule Localization
Jaeeun Jang1, Jihee Lee1, Kyoung-Rog Lee1, Jiwon Lee1, Minseo Kim1,
alternative to the cable-attached endoscopes since not only mitigating pain and fear of patients but also acquiring additional information about unexplained lesions for accurate diagnoses. Nevertheless, their applicabili
Yongsu Lee1, Joonsung Bae2, Hoi-Jun Yoo1 KAIST, Daejeon, Korea Kangwon
ISSCC 2017 Session 3 Digital Processors
A 1920×1080 30fps 2.3TOPS/W Stereo-Depth Processor for Robust Autonomous Navigation
Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin Kempke, Shijia Yang,
realizing autonomous navigation on micro-aerial vehicles (MAVs). The state-of-the-art semi-global matching (SGM) algorithm has become favored for its high accuracy. In particular, it effectively handles low texture regio
Zhengya Zhang, Ronald Dreslinski, Dennis Sylvester, David Blaauw, Hun
ISSCC 2017 Session 3 Digital Processors
A 60pJ/b 300Mb/s 128×8 Massive MIMO Precoder-Detector in 28nm FD-SOI
Hemanth Prabhu, Joachim Neves Rodrigues, Liang Liu, Ove Edfors
Further exploitation of the spatial domain, as in Massive MIMO (MaMi) systems, is imperative to meet future communication requirements [1]. Up-scaling of conventional 4×4 small-scale MIMO implementations to MaMi is prohi
Lund University, Lund, Sweden
ISSCC 2017 Session 3 Digital Processors
A 40nm Flash Microcontroller with 0.80μs FieldOriented-Control Intelligent Motor Timer and Functional Safety System for Next-Generation EV/HEV
Hayato Kimura1, Hideyuki Noda1, Hisaaki Watanabe1, Takashi Higuchi1,
Ryosaku Kobayashi2, Masayuki Utsuno1, Fumitake Takami1, Sugako Otani1, Masayuki Ito1, Yasuhisa Shimazaki1, Naoki Yada1, Hiroyuki Kondo1 Renesas Electronics, Tokyo, Japan Renesas System Design, Tokyo, Japan 1 2 Electric V