A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm

📋 论文概要

提出了一款96核处理器，采用6个小芯片3D堆叠在有源中介层上，实现了0.6ns/mm的延迟和3Tb/s/mm²的芯片间互连，总性能达220GOPS。同时集成了开关电容电压调节器(SCVR)实现快速DVFS和IR drop缓解。

💡 主要创新点

• 采用有源中介层实现6个小芯片的3D堆叠，大幅提升芯片间互连带宽和能效
• 集成SCVR和快速反馈控制器，实现<10ns步进响应的DVFS和IR drop补偿
• 通过3D堆叠和高效互连，在156mW/mm²功耗密度下达到82%的峰值效率

🏷 关键词

📄 原文摘要

which is finally delivered to the chiplet through a micro-bump face-to-face power grid (Fig. 2.3.7). The SCVR input voltage (up to 2.5V) reduces total input current and the required number of power IOs in the package. Each SCVR is supervised by a central clock-frequency and feedback controller to allow fast DVFS and IRdrop mitigation (<10ns step response). Pascal Vivet1, Eric Guthmuller1, Yvain Thonnart1, Gael Pillonnet1, Guillaume Moritz1, Ivan Miro-Panadès1, Cesar Fuguet1, Jean Durupt1, Christian Bernard1, Didier Varreau1, Julian Pontes1, Sebastien Thuries1, David Coriat1, Michel Harrand1, Denis Dutoit1, Didier Lattard1, Lucile Arnaud1, Jean Charbonnier1, Perceval Coudrain1, Arnaud Garnier1, Frederic Berger1, Alain Gueugnot1, Alain Greiner2, Quentin Meunier2, Alexis Farcy3, Alexandre Arriordaz4, Severine Cheramy1, Fabien Clermidy1 Figure 2.3.3 illustrates the microarchitecture of the source-synchronous 3D-plugs

👥 作者与机构

Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and, 156mW/mm2 @ 82%-Peak-Efficiency DC-DC Converters