ISSCC 2020
Session 1
AI / ML
The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design Jeffrey Dean
The past decade has seen a remarkable series of advances in machine learning, and in particular deeplearning approaches based on artificial neural networks, to improve our abilities to build more accurate systems across
ISSCC 2020
Session 1
Plenary
Fertilizing AIoT from Roots to Leaves Kou-Hung Lawrence Loh Senior Vice President & Corporate Strategy Officer
IoT with artificial intelligence, AIoT, enriches everything around the world. The application space is unlimited, ranging from fundamental research, enterprise, industry, transportation, services, and personal daily life
ISSCC 2020
Session 1
Plenary
Future Scaling: Where Systems and Technology Meet Nadine Collaert
In a smart society where everything will be connected, an avalanche of data is coming toward us, with numbers going to several hundreds of zettabytes per year by 2025! This data will need to be distributed, stored, compu
ISSCC 2020
Session 1
Plenary
The Future of Computing: Bits + Neurons + Qubits
Abstract The laptops, cell phones, and Internet applications commonplace in our daily lives are all rooted in the idea of zeros and ones – in bits. This foundational element originated from the combination of mathematics
ISSCC 2020
Session 10
RF & Wireless
A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR
Achieving <-157.5dBc/Hz OB Noise Gengzhen Qi1, Haijun Shao1, Pui-In Mak1, Jun Yin1, Rui P. Martins1,2 University of Macau, Macau, China, 2University of Lisboa, Lisbon, Portugal 1 For the sub-6GHz 5G New Radio (5G-NR), mo
ISSCC 2020
Session 10
RF & Wireless
A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation
A key aspect of 5G systems is supporting multiband and multistandard applications. Depending on operating conditions, this requires high in-band dynamic range and/or low noise floor at specific out-of-band (OOB) frequenc
ISSCC 2020
Session 10
RF & Wireless
A 12nm CMOS RF Transceiver Supporting 4G/5G UL MIMO
Mohammed Hassan2, Chi-Tsan Chen1, Chao-Wei Wang1, Yen-Chuan Huang1, Li-Han Hung1, Wei-Hao Chiu1, Anson Lin1, Bo-Yu Lin1, Arnaud Werquin2, Chien-Cheng Lin1, Yen-Horng Chen1, Jen-Che Tsai1, Yuan-Yu Fu1, Bernard Tenbroek2,
ISSCC 2020
Session 10
RF & Wireless
A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax
EVM Floor in 55nm CMOS Eric Lu1, Wen-Kai Li2, Zhiming Deng1, Edris Rostami1, Pi-An Wu2, Keng-Meng Chang2, Yu-Chen Chuang2, Chang-Ming Lai2, Yang-Chuan Chen1, Tzu-Hsuin Peng2, Tzung-Chuen Tsai2, Hui-Hsien Liu2, Chien-Chih
ISSCC 2020
Session 10
RF & Wireless
A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications
Bassam Khamaisi1, Elan Banin2, Eli Borokhovich2, Nahum Kimiagarov2, Phillip Skliar2, Rotem Banin1, Sarit Zur2, Sebastian Reinhold4, Smadar Bruker2, Tzvi Maimon1, Uri Parker2, Ofir Degani1 Intel, Haifa, Israel, 2Intel, Pe
ISSCC 2020
Session 10
RF & Wireless
A 4G/5G Cellular Transmitter in 12nm FinFET with Harmonic Rejection
Radio (NR) technology provides much higher data rate and system capacity compared to 4G LTE. This is achieved, among other techniques, by increasing the maximum channel bandwidth per component carrier (CC) from 20MHz in
ISSCC 2020
Session 10
RF & Wireless
A 0.26mm2 DPD-Less Quadrature Digital Transmitter With <-40dB EVM Over >30dB Pout Range in 65nm CMOS
based on RF digitalto-analog converters (DAC) are optimal for wireless transmitters in CMOS due to the small chip area, low power consumption, and ability to evolve with scaling of the transistor feature size. A DTX inte
ISSCC 2020
Session 10
RF & Wireless
A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS
Next-generation phased-array systems with large modulated bandwidths (BW) and high energy efficiency will enable Gb/s wireless communications. The spatial signal processing at this large scale using state-of-the-art phas
ISSCC 2020
Session 11
Power Management
A Direct 12V/24V-to-1V 3W 91.2%-Efficiency Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate Regulation
Texas Instruments, Santa Clara, CA 1 2 In industrial and automotive applications, 12V/24V power systems are widely used. In such systems, high step-down DC-DC converter is highly desirable to deliver a wide range of curr
ISSCC 2020
Session 11
Power Management
A Fully Integrated Resonant Switched-Capacitor Converter with 85.5% Efficiency at 0.47W Using On-Chip Dual-Phase Merged-LC Resonator
Fully integrated power management is important for a variety of applications spanning performance and mobile computing, embedded systems, and communications. However, monolithic integration has been elusive due to the li
ISSCC 2020
Session 11
Power Management
A One-Step 325V to 3.3-to-10V 0.5W Resonant DC-DC Converter with Fully Integrated Power Stage and 80.7% Efficiency
disabled after a fixed delay. It discharges the HSSet and HSReset nodes to prepare the level shifter for the next signal transmission. Due to measured slew rates as high as 20V/ns, a common-mode blanking circuit is used
ISSCC 2020
Session 11
Power Management
A 48-to-80V Input 2MHz Adaptive ZVT-Assisted GaNBased Bus Converter Achieving 14% Light-Load Efficiency Improvement
In modern hybrid electric vehicles, wide-input-range intermediate bus converters (IBCs) are essential in 48V power systems [1]. To increase the power efficiency, e-mode GaN FETs have been adopted in the IBCs [2, 3], as t
ISSCC 2020
Session 11
Power Management
A 2-Phase Soft-Charging Hybrid Boost Converter with Doubled-Switching Pulse Width and Shared Bootstrap Capacitor Achieving 93.5% Efficiency at a Conversion Ratio of 4.5 and vice versa in state-2 (at t3). As VDR34 is reused to charge C5 and C6, an additional drop on VDR34 will occur at t1 and t3. However, thanks to the proposed topology, M5 and M6 are relatively small since they have low voltage stress and small high-side (HS) currents (to be explained next). This reduces both the sizes of C5 and C6, and the VDR34 drop.
Figure 11.5.4 normalizes the power losses of the proposed HB to those of a 2PCB, with CR=4.5. We choose both the same inductor DCR and switch on-resistance (RON) for the two topologies. However, all the switches in 2P-CB
ISSCC 2020
Session 11
Power Management
A 1.46mm2 Simultaneous Energy-Transferring SingleInductor Bipolar-Output Converter with a Flying Capacitor for Highly Efficient AMOLED Display in 0.5µm CMOS Sung-Wan Hong
being more widely used in various electronic devices. As the display is one of the modules that consumes the largest portion of the power in electronic devices, displays must be designed to operate with a higher efficien
ISSCC 2020
Session 11
Power Management
A Voltage-Tolerant Three-Level Buck-Boost DC-DC Converter with Continuous Transfer Current and Flying Capacitor Soft Charger Achieving 96.8% Power Efficiency and 0.87µs/V DVS Rate
Dongsu Kim, Jaeyeol Han, Jun-Suk Bang, Yumi Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho Samsung Electronics, Hwaseong, Korea In recent years, buck-boost converters have been widely utilized for batte
ISSCC 2020
Session 11
Power Management
A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries
Taehwang Kong2, Sang-Ho Kim2, Sungyong Lee2, Michael Choi2, Jongshin Shin2, Gyu-Hyeong Cho1, Hyun-Sik Kim1 KAIST, Daejeon, Korea Samsung Electronics, Hwaseong, Korea 1 2 As internet-of-things (IoT) devices continue to be
ISSCC 2020
Session 12
Wireline I/O
A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control
stringent demands on the bandwidth and energy efficiency of data center interconnects, spurring the development of several 400G Ethernet standards [1]. Siliconphotonics-based solutions are of particular interest for low
ISSCC 2020
Session 12
Wireline I/O
A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications
Angelo Palladino1, Antonio Santipo1, Lorenzo Gerosa1, Matteo Repossi1, Gianluca Catrini2, Marta Campo2, Francesco Radice1, Andrea Diodato1, Roberto Pelleriti2, Daniele Baldi1, Laura Tarantini1, Luca Maggi1, Gianluca Rada
ISSCC 2020
Session 12
Wireline I/O
A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters
attention for constructing large-capacity optical core/metro networks and even data center interconnects. Data rates in the next generation of coherent optical transmission systems are expected to exceed 400Gb/s, for whi
ISSCC 2020
Session 12
Wireline I/O
A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver
DACs with an analog bandwidth (BW) of at least 50GHz to support advanced modulation schemes. CMOS-based DACs are preferred because they support monolithic integration of the DSP and DAC, but the achievable sampling rate
ISSCC 2020
Session 13
Memory
A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique pairs for low input offset to reduce a random dopant fluctuation. In order to reduce an input offset, the error amplifier designs that DC gain is above 74dB with all PVT variations. The Monte-Carlo simulation shows the variation is decreased by 46.9%, comparing to conventional one.
Sunghwa Ok, Jongwoo Kim, Kayoung Cho, Hyunchul Lee, Geonu Kim, Kangwoo Park, Kwanho Kim, Heejoo Lee, Sooyeol Chai, Chankeun Kwon, Hanna Cho, Chanhui Jeong, Yujin Yang, Jayoon Goo, Jangwon Park, Juhyeong Lee, Heonki Kim,
ISSCC 2020
Session 13
Memory
A 22nm 32Mb Embedded STT-MRAM with 10ns Read
Interference Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Chieh-Pu Lo, Meng-Chun Shih, Kuei-Hung Shen, Harry Chuang, Tsung-Yung Jonathan Chang TSMC, Hsinchu, Taiwan STT-MRA
ISSCC 2020
Session 13
Memory
A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices
Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Meng-Fan Chang National Tsing Hua University, Hsinchu, Taiwan Many security-aware mobile devices, using the secure hash
ISSCC 2020
Session 13
Memory
A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs
Sanad Bushnaq1, Takuyo Kodama1, Yuki Ishizaki1, Yoko Deguchi1, Akio Sugahara1, Akihiro Imamoto1, Norichika Asaoka1, Ryosuke Isomura1, Takaya Handa1, Junichi Sato2, Hiromitsu Komai1, Atsushi Okuyama1, Naoaki Kanagawa1, Ya
ISSCC 2020
Session 14
AI / ML
A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS
is a strong requirement for always-on speech interfaces in wearable and mobile devices, such as Voice Activity Detection (VAD) and Keyword Spotting (KWS) [1-5]. A KWS system is used to detect specific wake-up words by sp
ISSCC 2020
Session 14
AI / ML
A 65nm 24.7µJ/Frame 12.3mW Activation-SimilarityAware Convolutional Neural Network Video Processor
Zhe Yuan1,2, Yixiong Yang1, Jinshan Yue1,2, Ruoyang Liu1, Xiaoyu Feng1, Zhiting Lin3, Xiulong Wu3, Xueqing Li1, Huazhong Yang1, Yongpan Liu1 Tsinghua University, Beijing, China Pi2star Technology, Beijing, China 3 Anhui
ISSCC 2020
Session 14
AI / ML
A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse
University, Hsinchu, Taiwan 1 2 Computing-in-Memory (CIM) is a promising solution for energy-efficient neural network (NN) processors. Previous CIM chips [1-4] mainly focus on the memory macro itself, lacking insight on
ISSCC 2020
Session 15
AI / ML
A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and ChargeSharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications
Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li TSMC, Hsinchu, Taiwan Despite recent advances, low-voltage operation remains one of the key approaches for
ISSCC 2020
Session 15
AI / ML
A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips
Wei-Hsing Huang1, Yung-Ning Tu1, Ruhui Liu1, Pei-Jung Lu1, Ta-Wei Liu1, Jing-Hong Wang1, Zhixiao Zhang1, Hongwu Jiang3, Shanshi Huang3, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Shyh-Shyuan Sheu
ISSCC 2020
Session 15
AI / ML
A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications
computations and reduces off-chip weight access to reduce energy consumption and latency, specifically for AI edge devices. Prior CIM approaches demonstrated tradeoffs for area, noise margin, process variation and weight
ISSCC 2020
Session 15
AI / ML
A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices
Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang,
ISSCC 2020
Session 15
AI / ML
A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips multiplication results (PL"="IN[1:0]"⋅ W) to HGBLB.
Jing-Hong Wang1, Ta-Wei Liu1, Ssu-Yen Wu1, Ruhui Liu1, Yen-Chi Chou1, Zhixiao Zhang1, Syuan-Hao Sie1, Wei-Chen Wei1, Yun-Chen Lo1, Tai-Hsing Wen1, Tzu-Hsiang Hsu1, Yen-Kai Chen1, William Shih1, Chung-Chuan Lo1, Ren-Shuo
ISSCC 2020
Session 16
Data Converters
A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration
consumption enable direct RF sampling, more integration, flexibility and lower cost for communication, instrumentation and other applications. The state of the art of interleaved RF converters enables up to 10GS/s with 1
ISSCC 2020
Session 16
Data Converters
A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input
University of Lisboa, Lisbon, Portugal 1 2 The ever-increasing data traffic in wireline communication systems has led to the demand for high-speed ADCs with a large input BW. Time-interleaved SAR ADCs with a large interl
ISSCC 2020
Session 16
Data Converters
A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation
Chi-Hang Chan1, Jan Craninckx2, Rui P. Martins1,3 University of Macau, Macau, China imec, Leuven, Belgium 3 University of Lisboa, Lisbon, Portugal 1 2 Multi-GS/s ADCs are key blocks for ADC-based serial links and mm-wave
ISSCC 2020
Session 16
Data Converters
A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme
With the increasing demand for next-generation communication, the trend of developing wide-bandwidth, high-resolution ADCs has emerged, where pipelined SAR (PIPE-SAR) ADCs [1-2] have become popular owing to their excelle
ISSCC 2020
Session 16
Data Converters
A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation
University of Texas, Austin, TX 1 2 As with any ADC with a front-end S/H, the SAR ADC suffers from a fundamental SNR challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor has to be suffi
ISSCC 2020
Session 16
Data Converters
An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter
Donald Paterson4, Asha Ganesan1, Yunzhi Dong4, Wenhua Yang4, Yue"Yin1, Zhao Li1, Prawal Shrestha4, Athreya Gopal5, Aathreya Bhat4, Shanthi Pavan6 Analog Devices, Toronto, Canada, 2Analog Devices, San Diego, CA Analog Dev
ISSCC 2020
Session 16
Data Converters
A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS
A low-power, wide-bandwidth, and high-dynamic-range (DR) ADC is one of the critical building blocks in a wireless receiver design, in which a continuous-time delta-sigma modulator (CT DSM) has become a popular choice. Ho
ISSCC 2020
Session 17
Clocking & PLLs
A 66fsrms Jitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking
substantial increase in mobile data-rates, enabled by the 5G standard, calls for significantly lower integrated jitter of the local oscillator with respect to previous generations, with requirements below 90fs rms for mi
ISSCC 2020
Session 17
Clocking & PLLs
A 18.6-to-40.1GHz 201.7dBc/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting
The development of millimeter-wave (mmW) multiple-band systems for the 5G wireless and point-to-point backhaul communication requires ultra-wideband signal sources with low phase noise. However, with increasing parasitic
ISSCC 2020
Session 17
Clocking & PLLs
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
oscillators for 5G wireless transceivers require rms integrated jitter below 100fs to enable spectrally efficient modulation schemes, such as high-order quadrature amplitude modulation (QAM), at millimeter-wave carrier f
ISSCC 2020
Session 17
Clocking & PLLs
A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM
Ireland 1 2 Sub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular for 5G millimeter-wave (mmW) frequency generation [1,2] due to their ability to achieve ultra-low jitter (<100fs). How
ISSCC 2020
Session 17
Clocking & PLLs
A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth
continuous-wave (FMCW) radars are a viable solution for high-resolution indoor localization and tracking applications. The fast saw-tooth FMCW chirp needs to be synthesized with a short ramp time, large chirp bandwidth (
ISSCC 2020
Session 17
Clocking & PLLs
A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz
Chao Fan , Jun Yin , Chee-Cheow Lim , Pui-In Mak , Rui P. Martins 1 1 1 1 1,2 University of Macau, Macau, China University of Lisboa, Lisbon, Portugal 1 2 Low-power mm-wave sensors using an FMCW radar technology are open
ISSCC 2020
Session 18
Power Management
A Self-Health-Learning GaN Power Converter Using OnDie Logarithm-Based Analog SGD Supervised Learning and Online TJ-Independent Precursor Measurement
As GaN technology proliferates in modern power electronics, reliability of GaNbased circuits has become the biggest hurdle for commercialization. Sustaining largest voltage and current stresses in power circuits, power d
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