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ISSCC 2020Session 23 · ANALOG TECHNIQUES IIAnalog Circuits

A 41µW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation

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📋 论文概要

该论文提出了一种采用电容退化技术和非线性斜率因子补偿的动态放大器,用于流水线ADC中的残差放大器,在41µW超低功耗下实现了16MS/s采样率和99.2dB SFDR的高线性度,解决了传统闭环放大器功耗高的问题。

💡 主要创新点

核心指标
41µW功耗, 16MS/s采样率, 99.2dB SFDR
重要性
发表年份
ISSCC 2020

🏷 关键词

动态放大器电容退化非线性斜率因子补偿低功耗高线性度

📄 原文摘要

performance in analog front-ends and ADCs must have sufficiently low noise and high linearity to achieve overall system performance targets. Achieving the target noise level requires a certain amount of power, but nonlinearity can be improved by analog or digital techniques. Residue amplifiers used in pipelined ADCs have been improved to dissipate low power, preserving their linearity. Traditionally, closed-loop amplifiers with high open loop-gain are used for the residue amplifiers [1], but they require static current, thus degrading power efficiency. To improve the power efficiency of the residue amplifier, dynamic amplifiers have been investigated [2-4], which allow using only the required bandwidth, thus minimizing the power consumption for

👥 作者与机构

Yunhong Kim1,2, Sungsik Park1,2, Seungwoo Song1, Sangwoo Lee1,

MoonHyung Jang1, Changuk Lee1, Youngcheol Chae1 Yonsei University, Seoul, Korea Samsung Electronics, Hwaseong, Korea 1 2 The amplifiers used to improve the noise

分类:Analog Circuits · 年份:ISSCC 2020