A 134µW 24kHz-BW 103.5dB-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC

📋 论文概要

该论文提出了一种用于音频应用的高能效连续时间ΔΣ调制器，通过在第一积分器中使用斩波负电阻和三电平FIR DAC，实现了134µW功耗、24kHz带宽和103.5dB动态范围，解决了传统CTDSM在低功耗下线性度和能效不足的问题。

💡 主要创新点

• 提出斩波负电阻技术，补偿有源RC积分器的非理想性，提高线性度并降低功耗。
• 采用三电平FIR DAC，减少带内噪声和失真，进一步提升能效。

🏷 关键词

📄 原文摘要

Audio applications require a high-resolution ADC with a dynamic range (DR) of more than 100dB. A continuous-time delta-sigma modulator (CTDSM) is widely used to realize such ADCs and requires high energy efficiency for battery-powered devices [1-5]. This paper presents a more efficient, highly linear CTDSM architecture for audio applications. The first integrator of the CTDSM uses a chopped negative-R in conjunction with a tri-level FIR DAC to increase energyefficiency. Non-idealities of an active-RC integrator are compensated using a negative-R at the virtual ground of the integrator, and the negative-R is then chopped to remove its 1/f noise at a notch frequency of the feedback FIR filter. A 6-tap, tri-level FIR DAC is realized with a resistive non-return-to-zero (NRZ) DAC whose inter-symbol-interference (ISI) is kept less than -120dB. As a result, this work achieves 99.4dB SNDR, 101dB SNR, 103.5dB DR, and 110.2dB SFDR in a

👥 作者与机构

MoonHyung Jang, Changuk Lee, Youngcheol Chae

Yonsei University, Seoul, Korea