Lakefield and Mobility Compute: A 3D Stacked 10nm and

📋 论文概要

Lakefield处理器采用Foveros 3D堆叠技术，将10nm和22FFL工艺的芯片异构集成在12×12mm2、1mm厚的封装中，实现了小型化移动计算平台。解决了高性能与小型化之间的矛盾。

💡 主要创新点

• 采用Foveros 3D堆叠技术实现异构芯片垂直集成，显著减小封装面积和厚度。
• 结合10nm高性能计算die和22FFL低功耗I/O die，实现混合计算架构。
• 采用封装上封装（PoP）内存集成，进一步节省空间。

🏷 关键词

📄 原文摘要

Wilfred Gomes1, Sanjeev Khushu2, Doug B. Ingerly1, Patrick N. Stover3, Nasirul I. Chowdhury1, Frank O'Mahony1, Ajay Balankutty1, Noam Dolev3, Martin G. Dixon1, Lei Jiang1, Surya Prekke4, Biswajit Patra4, Pavel V. Rott1, Rajesh Kumar1 Intel, Hillsboro, OR, 2Intel, Santa Clara, CA, 3Intel, Chandler, AZ Intel, Bangalore, India 1 4 The Lakefield processor combines heterogeneous 3D die stacking also called Foveros, with hybrid computing to enable a new class of small form factor mobile products. The stacked die and implementation of the 3D package with PoP memory is shown in Fig. 8.1.1. The compute die is on Intel 10nm+ for powerperformance and includes the CPU, GPU, IPU, memory and display engine based on IP from the Icelake product family. It includes one Core™ and four Atom™ cores in a hybrid configuration connected using a cache-coherent fabric. Both core types are exposed to the operating system which selects the best core

👥 作者与机构

22FFL Hybrid Processor System in 12×12mm2, 1mm, Package-on-Package