Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications

📋 论文概要

本文提出了一种基于Via-Switch的新型FPGA架构，在65nm CMOS工艺中实现，并针对AI应用进行了架构扩展，旨在解决传统FPGA在AI推理和训练中的效率问题。

💡 主要创新点

• 采用Via-Switch作为非易失性可编程开关，实现高密度、低功耗的互连结构。
• 针对AI应用优化FPGA架构，支持高效的矩阵运算和数据流处理。

🏷 关键词

📄 原文摘要

Toshitsugu Sakamoto2, Jaehoon Yu1, Ryutaro Doi1, Yusuke Araki3, Hidetoshi Onodera3, Takashi Imagawa4, Hiroyuki Ochi4, Kazutoshi Wakabayashi5, Yukio Mitsuyama6, Tadahiko Sugibayashi2 Osaka University, Suita, Japan, 2NEC, Tsukuba, Japan Kyoto University, Kyoto, Japan, 4Ritsumeikan University, Kusatsu, Japan 5 NEC, Kawasaki, Japan, 6Kochi University of Technology, Kami, Japan 1 3 FPGAs are a suitable platform for implementing up-to-date machine learning algorithms and state-of-the-art AI applications including inference engines in embedded systems and training accelerators in cloud systems. Despite its short design turn-around time, the achievable performance is limited by the low area efficiency originating from field programmability [1-2]. Also, data transfer minimization in both amount and distance is essential for higher energy efficiency, but conventional FPGAs often require pipeline registers at SRAM and DSP I/Os

👥 作者与机构

Masanori Hashimoto1, Xu Bai2, Naoki Banno2, Munehiro Tada2,