A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips multiplication results (PL"="IN[1:0]"⋅ W) to HGBLB.

📋 论文概要

该论文提出了一种基于28nm 64Kb 6T SRAM的存内计算宏，支持8位乘加运算，用于AI边缘芯片。通过创新的电路设计，解决了传统架构中数据搬运带来的功耗和延迟瓶颈，实现了高效的多位MAC操作。

💡 主要创新点

• 提出了一种6T SRAM存内计算宏，支持8位输入和权重的乘加运算，无需额外模拟计算单元。
• 通过优化的位线计算方案，实现了高能效的多位MAC操作，适用于边缘AI推理。

🏷 关键词

📄 原文摘要

Jing-Hong Wang1, Ta-Wei Liu1, Ssu-Yen Wu1, Ruhui Liu1, Yen-Chi Chou1, Zhixiao Zhang1, Syuan-Hao Sie1, Wei-Chen Wei1, Yun-Chen Lo1, Tai-Hsing Wen1, Tzu-Hsiang Hsu1, Yen-Kai Chen1, William Shih1, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Nan-Chun Lien3, Wei-Chiang Shih3, Yajuan He2, Qiang Li2, Meng-Fan Chang1 1,2 1 1 1 1 National Tsing Hua University, Hsinchu, Taiwan University of Electronic Science and Technology of China, Chengdu, China 3 M31 Technology, Hsinchu, Taiwan 1 2 Advanced AI edge chips require multibit input (IN), weight (W), and output (OUT) for CNN multiply-and-accumulate (MAC) operations to achieve an inference accuracy that is sufficient for practical applications. Computing-in-memory (CIM) is an attractive approach to improve the energy efficiency (EFMAC) of MAC operations under a memory-wall constraint. Previous SRAM-CIM macros demonstrated a binary MAC [4], an in-array 8b W-merging with near-memory

👥 作者与机构

Xin Si , Yung-Ning Tu , Wei-Hsing Huang , Jian-Wei Su , Pei-Jung Lu ,