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该论文提出了一种带有kT/C噪声消除技术的13位40MS/s SAR ADC，通过集成噪声消除电路显著减小了采样电容，解决了传统大电容导致的输入驱动和参考缓冲器设计难题。
University of Texas, Austin, TX 1 2 As with any ADC with a front-end S/H, the SAR ADC suffers from a fundamental SNR challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor has to be sufficiently large (e.g. 3pF for a 13b ADC with 2Vpp swing). This, however, makes it very costly to design the ADC input driver and the reference buffer. The input driver and the reference buffer are the bottleneck nowadays. Their power, area, and design complexity can be an order of magnitude higher than the SAR ADC core. Since the root of the problem is the large input capacitor, it is highly desirable to figure out ways to reduce its size without incurring a kT/C noise penalty. In [1] a source follower is placed before the CDAC to prevent it from loading the ADC input, but this only shifts the burden to the source follower, which still needs to drive large sampling capacitors (7pF) limited by the kT/C noise. The source
Jiaxin Liu1, Xiyuan Tang2, Wenda Zhao2, Linxiao Shen2, Nan Sun2
Tsinghua University, Beijing, China