A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing cell is signed quasi-2-bit (3-level) or signed quasi-3-bit (7-level) accordingly.

📋 论文概要

本文实现了一款基于模拟ReRAM的存内计算芯片，通过全并行MAC计算单元和低压低功耗ADC设计，达到了78.4TOPS/W的能效，解决了传统架构的存储墙问题。

💡 主要创新点

• 利用ReRAM器件的多态电阻实现模拟域乘累加运算，支持256个电导状态。
• 设计了一种低功耗分段电容DAC与积分器结合的LPAR-ADC，高效读取电流信号。
• 采用全并行MAC计算架构，大幅提升吞吐量并降低功耗。

🏷 关键词

📄 原文摘要

on-chip ReRAM conductance could be quantified with 256 states at most. Qi Liu1, Bin Gao1, Peng Yao1, Dong Wu1, Junren Chen1, Yachuan Pang1, Wenqiang Zhang1, Yan Liao1, Cheng-Xin Xue2, Wei-Hao Chen2, Jianshi Tang1, Yu Wang1, Meng-Fan Chang2, He Qian1, Huaqiang Wu1 Figure 33.2.4 shows the structure and timing diagram of LPAR-ADC. LPAR-ADC is composed of three sub-modules: an integrator, a comparator and a segmentedcapacitor DAC (SC-DAC). The integrator consists of an operational amplifier (OPA) and an integrating capacitor. The integrator clamps the SL to VCLP and converts the SL current to an analog voltage signal. The SC-DAC generates a ramp voltage signal from VCLP to VDD. The comparator is used to compare the ramp voltage signal and the integrated voltage signal. The ADC workflow includes three phases: (1) PH1: Reset ADC via keeping the RST_integ/EN_integ switch ‘ON’, and the EN_DAC/EN_comp switch ‘OFF’. In this phase, SL and OUT_integ are clamped to

👥 作者与机构

According to the off-chip test on the same ReRAM stacks, the device conductance, could be tuned continuously. However, the on-chip ADC resolution limits that the