A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and ChargeSharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

📋 论文概要

该论文提出了一种采用5nm EUV和高迁移率沟道FinFET技术的135Mb SRAM，通过金属耦合和电荷共享写辅助电路来降低最小工作电压（VMIN），解决了先进工艺下SRAM因随机阈值电压波动导致的低电压操作难题。

💡 主要创新点

• 首次在5nm节点结合EUV和高迁移率沟道FinFET实现135Mb SRAM，提升晶体管性能与良率。
• 提出金属耦合和电荷共享写辅助技术，有效降低写操作所需电压，改善低电压下的写裕度。

🏷 关键词

📄 原文摘要

Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li TSMC, Hsinchu, Taiwan Despite recent advances, low-voltage operation remains one of the key approaches for power reduction. However, the continuous scaling of the SRAM bit cell, in advanced technologies, based on the transistor’s minimum geometry is accompanied by increased random threshold voltage variations that limit the SRAM’s minimum operating voltage (VMIN). The introduction of FinFET transistors has provided better short channel effects and less random dopant fluctuation, compared to prior bulk CMOS technology. However, the quantization of transistor sizing continues to be a major challenge for high-density 6T SRAM design. Figure 15.1.1(a) shows the layout of a high-density 6T SRAM bit cell in a 5nm EUV and high-mobility channel FinFET technology. In order to achieve a compact bit-cell

👥 作者与机构

Jonathan Chang, Yen-Huei Chen, Gary Chan, Hank Cheng,