← 返回论文列表 📄 下载原文 PDF  ISSCC 2020 · 6.7
ISSCC 2020Session 6 · ULTRA-HIGH-SPEED WIRELINEWireline I/O

An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文针对硅中介层上HBM的高密度通道间串扰问题,提出了一种结合前馈均衡(FFE)的串扰消除方案,并采用3D交错通道布局,实现了8Gb/s/µm的高吞吐量。该方案有效提升了通道密度而不显著增加功耗。

💡 主要创新点

重要性
发表年份
ISSCC 2020

🏷 关键词

HBM硅中介层串扰消除前馈均衡3D交错通道

📄 原文摘要

a silicon interposer technology to increase the number of I/O pins. Interfaces with the silicon interposer provide a higher throughput (Gb/s/µm) than other packaging technologies due to the high channel density. To increase the throughput further, either the per-pin data rate or the channel density should be increased. Since increasing the per-pin data rate requires a complex and powerhungry circuitry, increasing the channel density is an effective way to achieve the high throughput. However, a main problem with reducing the channel pitch is the crosstalk (XT) between adjacent lanes [1]. If the channels are stacked vertically for high channel density, the vertically adjacent channels become additional XT sources. There have been many research reports on the XT cancellation (XTC)

👥 作者与机构

Han-Gon Ko, Soyeong Shin, Jonghyun Oh, Kwanseo Park, Deog-Kyoon Jeong

Seoul National University, Seoul, Korea To meet the demand for high memory bandwidth, high-bandwidth memory (HBM) uses

分类:Wireline I/O · 年份:ISSCC 2020