技术领域

Wireline I/O

300 篇相关论文 (2008–2026)

ISSCC 2026 Session 8 Wireline I/O
A 72Gb/s/pin Single-Ended Simultaneous Bi-Directional Transceiver with C-Peaking Leakage Cancellation and Dual-Loop Hybrid Impedance Calibration for Chiplet Interfaces
Xuxu Cheng, Hongzhi Wu, Zhenghao Li, Weitao Wu, Xiongshi Luo, Yangyi Zhang, Quan Pan
Abstract This paper presents a 72Gb/s/pin single-ended simultaneously bi-directional (SBD) TRX in 28nm CMOS. Capacitive peaking leakage cancellation (CPLC) suppresses the high-frequency leakage due to the main and hybrid
Southern University of Science and Technology, Shenzhen, China
ISSCC 2026 Session 8 Wireline I/O
A 0.292pJ/b 56Gb/s/wire Capacitively Driven Simultaneous Bidirectional Transceiver with PVT/Mismatch Tracking for XSR and D2D Interfaces in 28nm CMOS
Kahyun Kim, Yoona Lee, Daehoon Na, Ha-Jung Park, Jeongeun Song, Woo-Seok Choi
Abstract A low-power (0.292pJ/b), high-bandwidth (56Gb/s/wire) single-ended capacitively driven simultaneous bi-directional (CD-SBD) TRX with PVT tolerance is proposed. Capacitive driving reduces power and self-interfere
Seoul National University, Seoul, Korea
ISSCC 2026 Session 8 Wireline I/O
A 112Gb/s PAM-4 SBD Transceiver with Mismatch-Compensated 2×VDD Hybrid and Two-Step Echo Canceller in 28nm CMOS
Huanfa Sun, Shangjie Wei, Yu Su, Chenyao Cao, Yujie Zeng, Yukun He, Zhouchi Duan, Guohe Zhang, Xiaoyan Gui
Abstract A 112Gb/s PAM-4 simultaneous bidirectional (SBD) transceiver in 28nm CMOS is presented. It features a hybrid with a 2×VDD stacked driver to restore signal swing, a joint delay and slew-rate matching scheme to el
Xi’an JiaoTong University, Xi’an, China
ISSCC 2026 Session 8 Wireline I/O
A 280mW 112Gb/s PAM-4/NRZ Transceiver for Low-Power IOs in 5nm FinFET Technology
Ullas Singh1, Kumar Thasari1, Nitin Nidhi1, Arvindh Iyer1, Saurabh Surana1, Batu Dayanik1, Yuanfang Li1, Mohammadamin To
Alberto Grassi1, Mehrdad Fahimnia1, Hiroshi Kimura2, Faramarz Bahmani2, Hao Chen2, Alex Wang2, Chen Zhao2, Yuan Fang2, Allen Chen3, Afshin Momtaz1, Namik Kocaman1 Broadcom, Irvine, CA, 2Broadcom, San Jose, CA, 3Broadcom,
ISSCC 2026 Session 8 Wireline I/O
A 112Gb/s 0.76pJ/b Reference-less Mixed-Signal PAM-4 CDR in 28nm CMOS
Zhaoyu Zhang*1,2, Yiqing Xu*1,2, Jian Liu1,2, Nanjian Wu1,2, Zhao Zhang1,2, Liyuan Liu1,2
*Equally Credited Authors (ECAs) 1 Abstract This paper presents a 112Gb/s mixed-signal reference-less PAM-4 CDR in 28nm CMOS. By proposing the hybrid architecture based on a symmetrical linear PD and a bang-bang PFD, a f
Institute of Semiconductors, Chinese Academy of Sciences, Beijing, Chi
ISSCC 2026 Session 8 Wireline I/O
A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS
Zhiwen Huang*1, Zhifei Wang*1, Bingyi Ye2, Tianchen Ye1, Dunshan Yu1, Wei Wang1,3, Weixin Gai1,3
*Equally Credited Authors (ECAs) 1 Abstract This work presents an 8-lane 112Gb/s/wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decoup
Peking University, Beijing, China, 2East China Normal University, Shan
ISSCC 2026 Session 8 Wireline I/O
A 0.23pJ/b 24Gb/s Modular D2D Interface With Zero Wake Penalty Clock Gating in 3nm
Ravi Shivnaraine1, Charles Boecker1, Eric Groen1, Simon Li1, Ping Lu1, Socrates Vamvakos1, Roxanne Vu1, Chris Hanke1, Sh
Marina Salik2, Kevin Bartholomew2, Sushmitha Reddy2, Alex Tessitore2, Aws Shallal2, Kalyan Nallaparaju2, Jin Liang2, Minhan Chen2, Shaishav Desai1 Microsoft, Sunnyvale, CA, 2Microsoft, Raleigh, NC 1 Abstract This work pr
ISSCC 2026 Session 8 Wireline I/O
A 32Gb/s 12.35Tb/s/mm2 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging
Wei-Chih Chen1, Mu-Shan Lin1, Chien-Chun Tsai1, Shenggao Li2, Wei-Shuo Lin1, Yu-Jie Huang1, Nai-Chen Cheng1, Yu-Chi Chen
Chin-Hua Wen1, Hsin-Hung Kuo1, Han-Tzung Ke1, Jie-Ren Huang1, Chang-Yi Li1, Sheng-Tsung Lai1, Shu-Chun Yang1, Kuan-Ting Chou1, Pei-Chen Chiou1, Tsung-Hsien Tsai1, Yi-Ting Chen1, Yen-Ming Chen1, Kenny Cheng-Hsiang Hsieh1
ISSCC 2026 Session 8 Wireline I/O
A 1.59pJ/b 112Gb/s PAM-4 and 1.06pJ/b 168Gb/s PAM-8 Resistor-Less 7-Bit SST DAC-Based Transmitter with 8-Tap FFE in 28nm CMOS
Yao-Hung Tsai, Ming-Han Chuang, Shen-Iuan Liu
Abstract A resistor-less 7b SST DAC-based TX with 8-tap FFE and 3 types of segments is presented to achieve low parasitic capacitance, compact area, and scaling friendliness. To reduce intersymbol-interference jitter at
National Taiwan University, Taipei, Taiwan
ISSCC 2026 Session 8 Wireline I/O
A 180-to-240Gb/s Analog-Intensive PAM-4 Transmitter with 0.70pJ/b Analog Power Efficiency in 65nm CMOS
Ziyi Lin, Haikun Jia, Wei Deng, Shitu He, Chang Liu, Zhihua Wang, Baoyong Chi
Abstract This paper presents a 180-240Gb/s analog-intensive PAM-4 transmitter in 65nm CMOS process. A three-stage cascaded 2-to-1 analog MUX (AMUX) is employed to reduce the complexity and therefore the parasitic capacit
Tsinghua University, Beijing, China
ISSCC 2026 Session 8 Wireline I/O
A 48Gb/s/lane 1.24Tb/s/mm UCIe-Compliant Die-to-Die Link Over 30mm Standard Package
Susnata Mondal*1, Sashank Krishnamurthy*1, Shuhei Yamada1, Zhaokai Liu2, Junyi Qiu1, Soumya Bose3, Zuoguo Wu2, Gerald Pa
work demonstrates a UCIe-S compliant die-to-die PHY at 48Gb/s/lane across 16 lanes, achieving 1.24Tb/s/mm shoreline BW density over a 30mm organic package at 1.2pJ/b, extendable to 56GT/s (1.13pJ/b). Circuit innovations
Intel, Hillsboro, OR, 2Intel, Santa Clara, CA, 3University of Californ
ISSCC 2026 Session 23 Wireline I/O
A 112Gb/s NRZ Heterodyne Detection 23ns Settled Burst-Mode RX with CD Suppression and Envelope Demodulation for 100G PON
Cheng Wang, Ye Gu, Gertjan Coudyzer, Shengpu Niu, Jing Zhang, Xin Yin
Abstract This work presents a burst-mode receiver based on an intensity modulation heterodyne detection scheme. SSB quadrature IF generation and envelope detection enhance baseband signal integrity and chromatic dispersi
imec - Ghent University, Ghent, Belgium
ISSCC 2026 Session 23 Wireline I/O
A 212Gb/s/λ 0.91pJ/b Direct-Drive O-Band Monolithic Coherent Transmitter Based on Carrier-Injection-Mode Mach-Zehnder Modulator
Antroy Roy Chowdhury1, Wahid Rahman1, Ahmed ElShater2, Tamer Ali2, Vladimir Stojanovic1,3
Abstract This work presents an O-band coherent direct-drive optical transmitter (OTX) in 45nm CMOS-SOI using a compact 0.4mm monolithically integrated forward-biased PIN-MZM. A multistage linear driver with shunt peaking
University of California, Berkeley, CA, 2MediaTek, Irvine, CA, 3Ayar L
ISSCC 2026 Session 23 Wireline I/O
A 6.4Tb/s 4.2pJ/b Co-Packaged Optics ASIC with Direct-Drive Integrated TIA and Retimed Segmented Mach-Zehnder Modulator Driver in 7nm FinFET
Mahdi Kashmiri, Ajay Yadav, Jin Namkoong, Behrooz Nakhkoob, Tony Kao, Shen Shen, Vaibhav Pandey, Kuan-Chang Chen, Jinho
4Tb/s co-packaged optics ASIC integrates 64 ingress path direct-drive TIAs and 64 egress path retimed segmented Mach-Zehnder modulator drivers in 7nm FinFET. The 7nm ASIC is 3D packaged with a photonics IC (PIC) and achi
Shayan Kazemkhani, Sang Young Kim, Simar Maangat, Bo Nguyen, Mike Robi
ISSCC 2026 Session 23 Wireline I/O
A 2×500Gb/s Monolithic Silicon-Photonic DWDM PAM-4 Transceiver in 45nm CMOS SOI
Ziang Xu*, Yalong Lin*, Jinxuan Jin*, Zhenkai Ye*, Dacheng Xu, Aolin Xu, Chaodi Sheng, Binwen Hong, Xiaojun Bi
*Equally Credited Authors (ECAs) Abstract This work presents a monolithic 2×5λ DWDM microring transceiver in 45nm CMOS SOI delivering 2×500Gb/s (100Gb/s PAM-4/channel). The transceiver features a low-noise TIA with Q-tam
Huazhong University of Science and Technology, Wuhan, China
ISSCC 2026 Session 23 Wireline I/O
A 2-Channel 800Gb/s Transceiver for Coherent-Lite Applications with <300ns Latency in 5nm FinFET
Marco Sosio1, Claudio Nani1, Enrico Monaco1, Nicola Ghittori1, Domenico Albano1, Alessio Di Pasquo1, Alessandro Bosi1, T
Fulvio Martinelli1, Victor Karam2, Devrishi Khanna2, Mehdi N. Khiarak2, Sasan Cyrusian3, Mehdi Davoodi3, Marco Garampazzi1, Nimesh N. Miral1, Fabio Giunco1, Ivan Fabiano1, Nicola Codega1, Claudio Asero1, Daniel L. Herbas
ISSCC 2026 Session 23 Wireline I/O
A 32Gb/s/λ 256Gb/s/Fiber Half-Rate Bandpass-Filtered Clock-Forwarding DWDM Optical Link in a 3D-Stacked 7nm EIC/65nm PIC Technology
Sanquan Song1, Nandish Mehta1, Nikola Nedovic1, Angad Rekhi1, Georgios Kalogerakis1, Li Xu1, Brian Zimmer1, Stephen G. T
Ward Lopes1, Benjamin G. Lee3, Thomas H. Greer III2, C. Thomas Gray2 Nvidia, Santa Clara, CA, 2Nvidia, Durham, NC, 3Nvidia, Ridgefield, CT 1 Abstract We present a 32Gb/s/λ dense wavelength division multiplexing bandpass-
ISSCC 2025 Session 7 Wireline I/O
A 60Gb/s NRZ Burst-Mode CDR with Cross-Injection Locking and Flash Phase Detector Achieving 0.13ns Reconfiguration Time in 28nm CMOS
Shangjie Wei, Renjie Tang, Chenyao Cao, Yu Su, Kanan Wang, Zhengyang Ye,
bandwidth and thermal power bottlenecks [1]. The increasing demands of the AI-centric data center impose more stringent requirements on low latency and high bandwidth [2]. Rapidly reconfigurable photonic switch networks
Huanfa Sun, Kun Fu, Xiaoyan Gui Xi’an JiaoTong University, Xi’an, Chin
ISSCC 2025 Session 7 Wireline I/O
A Reference-less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed
Xiaoteng Zhao, Yuhao Zhang, Hao Chang, Yilong Dong, Chenxi Han, Zekai Yang,
in applications that demand a continuous data rate due to their simplicity and cost-effectiveness, as they eliminate the need for an external reference [1-6]. The frequency acquisition (FA) speed of such CDRs is critical
Zhicheng Dong, Rong Zhou, Shubin Liu, Zhangming Zhu Xidian University,
ISSCC 2025 Session 7 Wireline I/O
A 2.06pJ/b 106.25Gb/s PAM-4 Receiver with 3-Tap FFE and 1-Tap Speculative DFE in 28nm CMOS
Yen-Po Lin, Yun-Cheng Jao, Wu-Hung Hsieh, Pen-Jui Peng
The increasing demand for I/O bandwidth in data center pushes the data rate of serial links up to 100Gb/s. Although ADC-based receivers have powerful and flexible DSP equalization that can compensate for >20dB channel lo
National Tsing Hua University, Hsinchu, Taiwan
ISSCC 2025 Session 7 Wireline I/O
A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET
Jaewon Lee1,2, Pier-Andrea Francese2, Matthias Brändli2, Thomas Morf2,
demand for higher communication bandwidth between processors through wired interconnects in large-scale servers has been driving the need to increase the perlane data rate beyond the current 112Gb/s. Recently demonstrate
Marcel Kossel2, Seoyoung Jang1, Gain Kim1 Daegu Gyeongbuk Institute of
ISSCC 2025 Session 7 Wireline I/O
A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET the CTLE_HF equivalent CM circuit in Fig. 7.4.3, the inductor coupling factor k can push the CM resonance frequency much higher than the cut-off frequency of the next stage’s SCC. Since the RLC network’s low-frequency impedance is small, which is given as a sum of the inductor ESR and a CM termination, the CTLE CM gain can be kept low over all frequency range.
Henry Park*1, Qaiser Nehal*1, Miguel Gandara1, Atharav Atharav1, Joonyeong Lee1, Another potential source of a ringing r
GPUs, long-reach high-speed interconnects with data rates of 100Gb/s or higher are widely demanded for many different applications such as Ethernet/Optical standards or PCIe 7.0. Despite the latest advances in DSP-based
Jengfeng Li2, Tamer Ali1 MediaTek, Irvine, CA 2 MediaTek, Hsinchu, Tai
ISSCC 2025 Session 7 Wireline I/O
A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS
Bingyi Ye1,2, Tianchen Ye1, Tianyuan Zhong1, Zhiwen Huang1, Lei Shen1,
Integrated Circuits, Beijing, China 1 2 Over the past few decades, process scaling and architecture advancements have led to an exponential increase in transceiver data rates. Recently, 224Gb/s DSP-based receivers (RXs)
Boyang Zhang1, Dunshan Yu1, Yandong He1, Weixin Gai1,3 Peking Universi
ISSCC 2025 Session 7 Wireline I/O
A 2.2pJ/b 212.5Gb/s PAM-4 Transceiver with >46dB Reach in 5nm FinFET
A. Mostafa1, A. Hassan1, A. Hsu2, A.K. Singh3, C.-H. Wu4, C.-R. Yang1,
D. Prabakaran3, D. Storaska5, D. Zhou1, D. Visani1, E. Hsiao1, F. Chu1, F. Khan1, F. Lu1, G. Cui1, G. Wang1, J. Natonio5, J. Deng1, J. Ding1, J. Guo1, J. Gu1, J. Zang1, L. Jiang1, K.-M. Lu4, M. Hasan1, M. Kelly6, M. H. K
ISSCC 2025 Session 7 Wireline I/O
An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS
Yechen Tian, Junjie Gu, Weitao He, Shuai Liu, Hao Xu, Na Yan
Multi-phase clock generation is among the most critical building blocks in high-speed wireline transceivers. The integrated jitter and phase error of the clocks often dictate the maximum available SNDR at higher frequenc
Fudan University, Shanghai, China
ISSCC 2025 Session 7 Wireline I/O
A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET
E-Hung Chen*1, Henry Park*2, Mohammed Abdullatif*2, Miguel Gandara2,
Ahmed ElShater2, Amr Khashaba2, Shih-Hao Huang1, Tsz-Bin Liu1, Atharav Atharav2, Joonyeong Lee2, Qaiser Nehal2, Mohamed Megahed2, Yusang Chun2, Cheng-En Shieh1, Vidhan Jolly2, SoonWon Kwon2, Hsin-Ta Chien1, Ke-Chung Wu1,
ISSCC 2024 Session 7 Wireline I/O
An 8b 6-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase Interpolator in 65nm CMOS Process receiving injections. Further, the quadrature outputs from the 4-phase signals from the RO are edge-combined using an XOR gate to produce differential outputs with twice the RO frequency as shown in Fig. 7.9.2.
Soumen Mohapatra, Emad Afshar, Zhiyuan Zhou, Deukhyoun Heo, Figure 7.9.3 shows a detailed circuit diagram of the ramp ge
capacitor current based on the differential input clocks to generate differential ramp signals. The internal loop within the replica bias sets the DC level of the ramp signal. To ensure the ramp’s linearity across proces
ISSCC 2024 Session 7 Wireline I/O
A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise
Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia,
Ahmed E. Abdelrahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu University of Illinois, Urbana, IL A low-jitter multi-phase clock generator is pivotal in high-speed serial link transceivers. With data rates surpas
ISSCC 2024 Session 7 Wireline I/O
A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS
Yen-Po Lin*, Pen-Jui Peng*, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh
serializer-deserializer (SerDes) transceivers for >100Gb/s data rates have been developed in recent years [1-4]. Differing from the medium-reach (MR) or long-reach (LR) applications, the XSR TRX targets <50mm traces for
National Tsing Hua University, Hsinchu, Taiwan *Equally Credited Autho
ISSCC 2024 Session 7 Wireline I/O
A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS
Liping Zhong*, Hongzhi Wu*, Yangyi Zhang*, Xuxu Cheng, Weitao Wu,
computing and artificial intelligence applications pushes wireline transceivers to higher data rates. DSP-based transmitters (TX) and receivers (RX) have achieved 224Gb/s [1-2], but unfortunately consume substantial power
Catherine Wang, Xiongshi Luo, Taiyang Fan, Dongfan Xu, Quan Pan Southe
ISSCC 2024 Session 7 Wireline I/O
A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE
Xiongshi Luo1, Xuewei You1, Zhenghao Li1, Hamed Mosalam1, Dongfan Xu1,
Taiyang Fan1, Hongchang Qiao1, Wentao Zhou1, Hongzhi Wu1, Liping Zhong1, Patrick Yin Chiang2, Quan Pan1 Southern University of Science and Technology, Shenzhen, China Fudan University, Shanghai, China 1 2 With the expone
ISSCC 2024 Session 7 Wireline I/O
A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and −74.2dBc Reference Spur
Yunbo Huang1, Yong Chen1, Zunsong Yang2, Rui P. Martins1,3, Pui-In Mak1
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 A ring oscillator (RO) based phase-locked loop (PLL) is a promising
University of Macau, Macau, China
ISSCC 2024 Session 7 Wireline I/O
A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS
Dirk Pfaff1, Muhammad Nummer1, Noman Hai2, Peter Xia2, Kai Ge Yang2,
Mohammad-Mahdi Mohsenpour1, Marc-Andre LaCroix1, Babak Zamanlooy3, Tom Eeckelaert1, Dmitry Petrov1, Mostafa Haroun1, Carson Dick2, Alif Zaman1, Haitao Mei1, Shahab Moazzeni1, Tahseen Shakir1, Carlos Carvalho1, Howard Hua
ISSCC 2024 Session 7 Wireline I/O
A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET
Marco Cusmai1, Noam Familia1, Elad Kuperberg1, Mohammad Nashash1,
Dovid Gottesman1, Daljeet Kumar2, Zvi Marcus1, Yeshayahu Horwitz1, Sagi Zalcman1, Jihwan Kim3, Sandipan Kundu3, Ilia Radashkevich1, Yoav Segal1, Dror Lazar1, Udi Virobnik1, Mike Peng Li4, Ariel Cohen1 Intel, Jerusalem, I
ISSCC 2024 Session 7 Wireline I/O
A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET
J. Q. Wang1, A. Tan1, A. Iyer1, A. Fan2, A. Farhoodfar1, B. Alnabulsi3, B. Smith3,
C. Loi4, C. R. Ho1, D. Cartina5, J. Riani1, J. Casanova1, K. Raviprakash1, L. Patra1, L. Wang1, M. Bachu1, S. Ray1, S. Chong4, S. Dallaire3, T. Nguyen1, T.-F. Wu2, V. Giridharan1, V. Gurumoorthy1, X. Ding4, Y. Yin1, Z. S
ISSCC 2023 Session 6 Wireline I/O
A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm the selected FFE setting, with proper shift operations involved. This approach minimizes the area and power overhead for the FFE multiplexing, while still covering a sufficient range of configurations for representative channels.
Jeonghyu Yang*, Eunji Song*, Seungwook Hong, Dongjun Lee, Sangwan Lee,
Hyunwoo Im, Taeho Shin, Jaeduk Han The FIR controller output and the N-bit shifted MSB signals are further upconverted by the following ten 8:4 serializers, producing a 40-bit data stream (TA4, TB4, and TC4 for the norma
ISSCC 2023 Session 6 Wireline I/O
A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS
Kai Sheng, Weixin Gai, Zeze Feng, Haowei Niu, Bingyi Ye, Hang Zhou
The ever-growing demands for high-bandwidth communications continuously push wireline links to operate at higher speeds. Recently reported transmitters (TXs) have achieved a data rate of more than 100Gb/s [1-6]. PAM-4 mo
Peking University, Beijing, China
ISSCC 2023 Session 6 Wireline I/O
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications one point. VREFPM is set slightly above h0, and VREFPN is set slightly under $h0 for the optimal point. In this work, a single-stage CTLE is implemented for an energy-efficient equalizer, and the second lock option is chosen.
Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park,
Youngwook Kwon, Chulwoo Kim Figure 6.6.4 shows the circuit implementation and the operation of the data recovery path. The detailed operation is illustrated as two phases (CK0,90) in simulated transient waveforms. A conv
ISSCC 2023 Session 6 Wireline I/O
A 37.8dB Channel Loss 0.6µs Lock Time CDR with Flash Frequency Acquisition in 5nm FinFET
Chien-Kai Kao, Shih-Che Hung, Tse-Hsien Yeh, Chen-Yu Hsiao
High-speed SerDes is accompanied by high channel loss. Channel loss is usually compensated by transmitter feed-forward equalization (FFE), receiver continuous time linear equalization (CTLE), and receiver decision-feedba
MediaTek, Hsinchu, Taiwan
ISSCC 2023 Session 6 Wireline I/O
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques
Kihwan Seong, Donguk Park, Gyeomje Bae, Hyunwoo Lee, Youngseob Suh,
Wooseuk Oh, Hyemun Lee, Juyoung Kim, Takgun Lee, Geonhoo Mo, Sukhyun Jung, Dongcheol Choi, Byoung-Joo Yoo, Sanghune Park, Hyo-Gyuem Rhew, Jongshin Shin Samsung Electronics, Hwasung, Korea Recently, the demand for multi-c
ISSCC 2023 Session 6 Wireline I/O
A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS
Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He
The ever-increasing demand for greater I/O bandwidth has pushed the transceiver data rate to 200Gb/s [1]. At this rate, the implementation of decision-feedback equalizers faces severe timing constraints. Discrete-time fe
Peking University, Beijing, China
ISSCC 2023 Session 6 Wireline I/O
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET detection can either use a low-latency short FFE to minimize peaking in the jitter transfer curve or use the main FFE/DFE output for very high loss channels (> 40dB).
Henry Park*1, Mohammed Abdullatif*1, Ehung Chen1, Ahmed Elmallah1,
Qaiser Nehal1, Miguel Gandara1, Tsz-Bin Liu2, Amr Khashaba1, Joonyeong Lee1, Chih-Yi Kuan2, Dhinessh Ramachandran1, Ruey-Bo Sun2, Atharav Atharav1, Yusang Chun1, Mantian Zhang1, Deng-Fu Weng2, Chung-Hsien Tsai2, Chen-Hao
ISSCC 2023 Session 6 Wireline I/O
A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology
Bo Zhang1, Anand Vasani1, Ashutosh Sinha2, Alireza Nilchi1, Haitao Tong1,
Lakshmi Rao1, Karapet Khanoyan1, Hamid Hatamkhani1, Xiaochen Yang1, Xin Meng1, Alexander Wong2, Jun Kim2, Ping Jing2, Yehui Sun2, Ali Nazemi1, Dean Liu2, Anthony Brewster1, Jun Cao1, Afshin Momtaz1 Broadcom, Irvine, CA B
ISSCC 2022 Session 6 Wireline I/O
A 50Gb/s PAM-4 Bi-Directional Plastic Waveguide Link with Carrier Synchronization Using PI-Based Costas Loop
Ha-Il Song1, Hanho Choi1,2, Jun young Yoo1, Hyo-Sup Won1, Cheong Min Lee1,
Huxian Jin1, Tai young Kim1, Woohyun Kwon2, Kyoohyun Lim1, Konan Kwon1, Chang-Ahn Kim1, Taeho Kim1, Jun Gi Jo1, Jake Eu1, Sean Park1, Hyeon-Min Bae2 Point2 technology, Seoul, Korea KAIST, Daejeon, Korea of the I-DCM conv
ISSCC 2022 Session 6 Wireline I/O
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS
G. Gangasani1, D. Hanson1, D. Storaska1, H. H. Xu1, M. Kelly1, M. Shannon1,
M. Sorna1, M. Wielgos1, P. B. Ramakrishna2, S. Shi3, S. Parker1, U. K. Shukla2, W. Kelly1, W. Su3, Z. Yu4 Marvell, Hopewell Junction, NY Marvell, Bangalore, India 3 Marvell, Shanghai, China 4 Marvell, Santa Clara, CA bet
ISSCC 2022 Session 6 Wireline I/O
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology
Namik Kocaman1, Ullas Singh1, Bharath Raghavan1, Arvindh Iyer1,
Kumar Thasari1, Saurabh Surana1, Jun Won Jung1, Jaehun Jeong1, Heng Zhang1, Anand Vasani1, Yonghyun Shim1, Zhi Huang1, Adesh Garg1, Hsiang-bin Lee1, Bo Wu2, Feifei Liu1, Ray Wang1, Matthew Loh2, Alex Wang2, Mario Caresos
ISSCC 2022 Session 6 Wireline I/O
A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS
Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He,
entertainment has never been fulfilled. Mixed-signal PAM-4 transceivers prevail over their ADC-DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high-loss links. Typically, a
Song Jia, Congcong Chen, Jiaqi Yu Peking University, Beijing, China Th
ISSCC 2022 Session 6 Wireline I/O
A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET
Z. Guo1, A. Mostafa1, A. Elshazly 1, B. Chen1, B. Wang1, C. Han1, C. Wang1,
D. Zhou1, D. Visani1, E. Hsiao1, F. Chu1, F. Lu1, G. Cui1, H. Zhang1, H. Wang1, H. Zhao1, J. Lin1, J. Gu1, L. Luo2, L. Jiang1, M. Singh1, M. Gambhir1, M. Hasan1, M. Wu1, M. J. Yoo1, P. Liu1, S. Kollu1, T. Ye2, X. Zhao2,
ISSCC 2022 Session 6 Wireline I/O
A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation
Yoav Segal1, Amir Laufer1, Ahmad Khairi1, Yoel Krupnik1, Marco Cusmai1,
Itamar Levin1, Ari Gordon1, Yaniv Sabag1, Vitali Rahinski1, Gadi Ori1, Noam Familia1, Stas Litski1, Tali Warshavsky1, Udi Virobnik1, Yeshayahu Horwitz1, Ajay Balankutty2, Shiva Kiran2, Samuel Palermo3, Peng Mike Li4, Ari
ISSCC 2022 Session 17 Wireline I/O
A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process
Amit Kumar Mishra1, Yifei Li2, Pawan Agarwal2, Sudip Shekhar1
MaxLinear, Carlsbad, CA 1 2 Increased data-rates and multi-lane SerDes implementations impose stringent conditions for CDRs to produce low-jitter clocking that is capable of managing frequency and phase offsets. Conseque
University of British Columbia, Vancouver, Canada