A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS

📋 论文概要

该论文提出了一种用于极短距离(XSR)应用的112Gb/s PAM-4收发器，采用了时间交错2b/3b ADC和非平衡波特率CDR架构，在28nm CMOS工艺下实现了2.16pJ/b的能效，解决了低损耗信道下高速串行通信的功耗优化问题。

💡 主要创新点

• 提出时间交错2b/3b ADC结构，在降低ADC分辨率的同时保持采样率，从而节省功耗。
• 采用非平衡波特率时钟数据恢复(CDR)技术，优化了时钟恢复的功耗和抖动性能。

🏷 关键词

📄 原文摘要

serializer-deserializer (SerDes) transceivers for >100Gb/s data rates have been developed in recent years [1-4]. Differing from the medium-reach (MR) or long-reach (LR) applications, the XSR TRX targets <50mm traces for in-package dieto-die communication and optical I/O interfaces for co-packaged optics (CPO). Such a channel presents <10dB Nyquist loss when delivering a 112Gb/s PAM-4 signal. As a result, the equalization complexity can be reduced to achieve better power efficiency. In this work, a power-efficient XSR TRX architecture is presented and realized in 28nm CMOS consuming 2.16pJ/b with under 8.5dB loss. Figure 7.7.1 shows the RX architecture. The 112Gb/s PAM-4 signal is first received by the on-die termination (ODT) with T-coil for broadband matching in the presence of ESD. The analog front-end (AFE) includes a CTLE to compensate the channel loss, followed

👥 作者与机构

Yen-Po Lin*, Pen-Jui Peng*, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh

National Tsing Hua University, Hsinchu, Taiwan *Equally Credited Authors (ECAs) Extra-short-reach (XSR)