A 32Gb/s 12.35Tb/s/mm2 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging

📋 论文概要

本文提出了一种边缘触发收发器（ETT），并集成在主动本地硅互连（aLSI）中，实现了类似UCIe的芯片间互连。该设计在3nm工艺下达到了32Gb/s的数据速率，同时实现了0.36pJ/b的能效和12.35Tb/s/mm²的面积效率，有效解决了高带宽密度和低功耗的芯片互连挑战。

💡 主要创新点

• 提出边缘触发收发器（ETT）结构，替代传统源同步或时钟转发方案，显著降低功耗并实现更紧凑的收发器设计。
• 将ETT集成在主动本地硅互连（aLSI）中，支持高密度Die-to-Die互连，优化了面积效率和能量效率。
• 在3nm先进工艺节点下实现了32Gb/s的单通道速率和0.07pJ/b的TX/RX功耗，整体能效达0.36pJ/b。

🏷 关键词

📄 原文摘要

Chin-Hua Wen1, Hsin-Hung Kuo1, Han-Tzung Ke1, Jie-Ren Huang1, Chang-Yi Li1, Sheng-Tsung Lai1, Shu-Chun Yang1, Kuan-Ting Chou1, Pei-Chen Chiou1, Tsung-Hsien Tsai1, Yi-Ting Chen1, Yen-Ming Chen1, Kenny Cheng-Hsiang Hsieh1 TSMC, Hsinchu, Taiwan, 2TSMC, San Jose, CA 1 Abstract This paper presents edge-triggered transceivers (ETT), enabling a 32Gb/s UCIe-like chiplet interconnect when integrated within an active local silicon interconnect (aLSI). The ETT achieves power consumption of 0.07pJ/b and supports compact top-die TX/RX designs while optimizing 0.36pJ/b energy efficiency and 12.35Tb/s/mm2 area bandwidth density. It demonstrates a 32Gb/s die-to-die link at 0.75V with 20.46ps eye width (65% UI) and 530mV eye height across 64 lanes in a 3nm CMOS process. The rapid growth of data-centric computing, fueled by internet traffic, AI, and GPUs/TPUs, is driving demand for high-bandwidth interconnect solutions. Universal Chiplet Interconnect

👥 作者与机构

Wei-Chih Chen1, Mu-Shan Lin1, Chien-Chun Tsai1, Shenggao Li2, Wei-Shuo Lin1, Yu-Jie Huang1, Nai-Chen Cheng1, Yu-Chi Chen1, Wen-Hung Huang1,