A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET

📋 论文概要

本文提出了一种基于时间域ADC的离散多音（DMT）线缆接收器数据通路，在5nm FinFET工艺下实现了112Gb/s的数据率和353mW的功耗，解决了高速有线互连中ADC接收器功耗高的问题。

💡 主要创新点

• 采用时间域ADC替代传统电压域ADC，降低功耗并提高能效。
• 使用离散多音（DMT）调制技术，提高频谱效率并简化均衡。
• 在5nm FinFET工艺中实现低功耗高速接收器数据通路。

🏷 关键词

📄 原文摘要

demand for higher communication bandwidth between processors through wired interconnects in large-scale servers has been driving the need to increase the perlane data rate beyond the current 112Gb/s. Recently demonstrated analog-to-digital converter (ADC)-based receiver (RX) prototypes with >100Gb/s data rate typically employ a parallel feed-forward equalizer (FFE) with a large number of taps, 1-tap decision feedback equalizer (DFE) [1-5], and maximum likelihood sequence estimator (MLSE) as option [6-8]. As the data rate grows exponentially, the pulse response length and the number of corresponding inter-symbol interference (ISI) cursors increase accordingly [5,8]. As the length of the pulse response gets doubled, the FFE tap count also needs to be increased

👥 作者与机构

Jaewon Lee1,2, Pier-Andrea Francese2, Matthias Brändli2, Thomas Morf2,

Marcel Kossel2, Seoyoung Jang1, Gain Kim1 Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea 2 IBM Research Europe, Rüschlikon, Switzerland 1 The growing