A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications one point. VREFPM is set slightly above h0, and VREFPN is set slightly under $h0 for the optimal point. In this work, a single-stage CTLE is implemented for an energy-efficient equalizer, and the second lock option is chosen.

📋 论文概要

本文提出了一种用于短距离应用的52Gb/s PAM-4波特率时钟数据恢复电路，采用基于模式的相位检测器实现低功耗和高效率。该设计在0.83pJ/b的能效下实现了52Gb/s的数据速率，解决了短距离高速互连中的时钟恢复和数据恢复问题。

💡 主要创新点

• 采用基于模式的相位检测器（Pattern-Based Phase Detector），利用数据模式信息进行相位检测，提高CDR的跟踪精度和稳定性。
• 实现了一种高效的四输入强臂锁存比较器，通过比较器决策时间差进行+1和-1解码，简化了数据恢复路径。

🏷 关键词

📄 原文摘要

Youngwook Kwon, Chulwoo Kim Figure 6.6.4 shows the circuit implementation and the operation of the data recovery path. The detailed operation is illustrated as two phases (CK0,90) in simulated transient waveforms. A conventional four-input strong-arm latch comparator is implemented, and the difference in decision time between COMPPM and COMPNM is used for $1 and +1 decoding. When data is +1, there is little voltage difference between the sum of VINP and VREFNM and the sum of VINN and VREFPM at the COMPPM. Then, output nodes PMP and PMN are slowly determined to be 1 and 0, or 0 and 1 depending on noise sources such as ISI, data jitter, clock jitter, and reflection. They may not even be determined (meta-stability) before the pre-charge action. Meanwhile, because there is a sufficient voltage difference between the sum of VINP and VREFPM and the sum of VINN and VREFNM at the COMPNM, output nodes NMP and NMN are quickly determined to be 1 and 0, respectively. For these

👥 作者与机构

Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park,