A 0.23pJ/b 24Gb/s Modular D2D Interface With Zero Wake Penalty Clock Gating in 3nm

📋 论文概要

本文提出一款在3nm工艺下实现的24Gb/s芯片间（D2D）接口，通过零唤醒惩罚时钟门控技术实现了0.23pJ/b的模拟PHY功耗，并支持模块化设计。该接口在20Gb/s下能效达到0.17pJ/b，端到端平均延迟4.2ns，误码率低于1e-18，解决了高性能D2D链路的能效与快速唤醒难题。

💡 主要创新点

• 提出零唤醒惩罚时钟门控技术，使接口在低功耗待机与快速唤醒间无额外延迟开销，显著提升能效。
• 采用模块化架构，支持大规模多通道（1680条）扩展，并在3nm工艺下实现极低功耗（0.23pJ/b）和低延迟（4.2ns）。

🏷 关键词

📄 原文摘要

Marina Salik2, Kevin Bartholomew2, Sushmitha Reddy2, Alex Tessitore2, Aws Shallal2, Kalyan Nallaparaju2, Jin Liang2, Minhan Chen2, Shaishav Desai1 Microsoft, Sunnyvale, CA, 2Microsoft, Raleigh, NC 1 Abstract This work presents a 3nm 24Gb/s D2D Interface achieving 0.23pJ/b (analog PHY power) and zero wake penalty clock gating and 0.17pJ/b at 20Gb/s. The PHY achieves a total endto-end average latency of 4.2ns (~25% analog macro). Measured performance demonstrates a worst-case bit-error rate, extrapolated to 1e-18 measured across 1680 lanes over PVT of 12pspp. The modular nature of this work allows flexibility in the construction of D2D links and natively supports asymmetric TX and RX bandwidths. Modern AI and compute systems increasingly rely on chiplet architectures and disaggregated designs, driving the need for die-to-die interconnect solutions that deliver high bandwidth, low active power, and minimal latency. Emerging standards such as UCIe

👥 作者与机构

Ravi Shivnaraine1, Charles Boecker1, Eric Groen1, Simon Li1, Ping Lu1, Socrates Vamvakos1, Roxanne Vu1, Chris Hanke1, Shankar Tangirala1, Wen Liu1,