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本文提出一种28nm CMOS工艺下实现106.25Gb/s PAM-4信号的混合信号接收机，采用3抽头FFE和1抽头推测DFE，通过1+0.5D脉冲整形技术减少切片器数量并缓解时序约束，达到2.06pJ/b的能效。该设计解决了ADC型接收机在较大节点下功耗较高的问题，满足数据中心对高带宽低功耗串行链路的需求。
The increasing demand for I/O bandwidth in data center pushes the data rate of serial links up to 100Gb/s. Although ADC-based receivers have powerful and flexible DSP equalization that can compensate for >20dB channel loss [1-5], the power consumption is not competitive when using process nodes larger than 16nm [6]. The mixed-signal receiver utilizing 1+0.5D pulse shaping can implement the speculative DFE for PAM-4 signals with fewer slicers [7]. It relieves the stringent timing constraint for the DFE with less power dissipation. However, to accomplish a 1+0.5D pulse response with minimum residual ISI, the TX FFE must be included [8]. It makes the adaptation loop for TRX link equalization more difficult. Another approach uses the RX FFE to fully eliminate h1 [9]. It avoids the DFE timing issue, but the AFE noise would be significantly increased by canceling the large amount of h1, degrading the BER performance. This paper presents a 106.25Gb/s PAM-4
Yen-Po Lin, Yun-Cheng Jao, Wu-Hung Hsieh, Pen-Jui Peng
National Tsing Hua University, Hsinchu, Taiwan