A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET the CTLE_HF equivalent CM circuit in Fig. 7.4.3, the inductor coupling factor k can push the CM resonance frequency much higher than the cut-off frequency of the next stage’s SCC. Since the RLC network’s low-frequency impedance is small, which is given as a sum of the inductor ESR and a CM termination, the CTLE CM gain can be kept low over all frequency range.

📋 论文概要

本文提出一种采用基于LC谐振器的连续时间线性均衡器（CTLE）和模拟数据路径延迟降低技术的DSP型112Gb/s PAM-4接收器，在4nm FinFET工艺下实现了超过52dB的损耗补偿，适用于长距离高速互连如以太网、光通信和PCIe 7.0等场景。

💡 主要创新点

• 提出基于LC谐振器的CTLE架构，有效提升高频补偿能力并降低功耗。
• 引入模拟数据路径延迟降低技术，优化信号传输时序，实现更高能效。

🏷 关键词

📄 原文摘要

GPUs, long-reach high-speed interconnects with data rates of 100Gb/s or higher are widely demanded for many different applications such as Ethernet/Optical standards or PCIe 7.0. Despite the latest advances in DSP-based wireline transceivers, the increasing complexity in networking systems requires a breakthrough in SerDes architecture for successful signal transmissions over long channels. This work presents an energy-efficient DSP-based 112Gb/s PAM-4 receiver with a novel CTLE architecture and analog data path latency reduction technique. The proposed ideas are also directly applicable to the upcoming PCIe 7.0 systems for 128GT/s. A continuous time linear equalizer (CTLE) is one of the most important components for all wireline interconnects. Historically, source-degenerated differential pairs were used for data

👥 作者与机构

Henry Park*1, Qaiser Nehal*1, Miguel Gandara1, Atharav Atharav1, Joonyeong Lee1, Another potential source of a ringing response from RXFE is shown in Fig. 7.4.3 by the

Jengfeng Li2, Tamer Ali1 MediaTek, Irvine, CA 2 MediaTek, Hsinchu, Taiwan 1 *Equally Credited Authors (ECAs) With rapid growth of AI accelerators and