A 180-to-240Gb/s Analog-Intensive PAM-4 Transmitter with 0.70pJ/b Analog Power Efficiency in 65nm CMOS

📋 论文概要

该论文提出一款180-240Gb/s模拟密集型PAM-4发射机，采用三级级联2-to-1模拟MUX降低复杂度和寄生电容，通过可重构4-tap FFE、电流注入和双T-coil技术提升输出摆幅与带宽，实现了0.70pJ/b的模拟能效。

💡 主要创新点

• 采用三级级联2-to-1模拟MUX，显著降低内部高速节点和输出节点的寄生电容，简化电路复杂度。
• 结合可重构4-tap FFE与电流注入技术，有效提升PAM-4输出摆幅。
• 引入双T-coil技术，扩展带宽并改善高频性能。

🏷 关键词

📄 原文摘要

Abstract This paper presents a 180-240Gb/s analog-intensive PAM-4 transmitter in 65nm CMOS process. A three-stage cascaded 2-to-1 analog MUX (AMUX) is employed to reduce the complexity and therefore the parasitic capacitance of both output and internal high-speed nodes. Reconfigurable 4-tap FFE, current injection, and dual T-coil techniques are proposed to enhance the output swing and the bandwidth. The transmitter achieves 0.70pJ/b analog energy efficiency at a 240Gb/s data rate. The rapid growth of applications such as artificial intelligence (AI) and high-performance computing (HPC) has driven strong demand for high-speed transceivers (TRXs) operating beyond 200Gb/s per channel. Several transmitter (TX) implementations in advanced CMOS FinFET processes exceeding 200Gb/s have been reported in [1]-[4]. However, design challenges still exist to pursue further higher data rates and higher energy efficiency. First,

👥 作者与机构

Ziyi Lin, Haikun Jia, Wei Deng, Shitu He, Chang Liu, Zhihua Wang, Baoyong Chi

Tsinghua University, Beijing, China