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ISSCC 2026Session 23 · NEXT-GENERATION OPTICAL TRANSCEIVERSWireline I/O7nm FinFET

A 6.4Tb/s 4.2pJ/b Co-Packaged Optics ASIC with Direct-Drive Integrated TIA and Retimed Segmented Mach-Zehnder Modulator Driver in 7nm FinFET

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文提出了一款6.4Tb/s的共封装光学ASIC,集成了64路直接驱动TIA和64路重定时分段马赫-曾德尔调制器驱动器,采用7nm FinFET工艺,实现了4.2pJ/b的能效,解决了AI集群中高带宽光互连的功耗和密度问题。

💡 主要创新点

核心指标
6.4Tb/s总带宽,4.2pJ/b能效,106.25Gb/s PAM-4 TIA灵敏度<-11dBm,BER<1E-9,TDEQ=1.48dB,ER=4.57dB
工艺节点
7nm FinFET
重要性
发表年份
ISSCC 2026

🏷 关键词

共封装光学直接驱动TIA分段马赫-曾德尔调制器7nm FinFETPAM-4

📄 原文摘要

4Tb/s co-packaged optics ASIC integrates 64 ingress path direct-drive TIAs and 64 egress path retimed segmented Mach-Zehnder modulator drivers in 7nm FinFET. The 7nm ASIC is 3D packaged with a photonics IC (PIC) and achieves an energy efficiency of 4.2pJ/b. At 106.25Gb/s, its PAM-4 TIA has a sensitivity better than -11dBm and a BER floor better than 1E-9. The transmitted PAM-4 optical eye achieves a TDEQ of 1.48dB and an extinction ratio of 4.57dB. Optical interconnects are gaining importance for the high-bandwidth communication needs of the scale-out AI clusters, replacing the pluggable modules. Co-packaged optics (CPO) is a heterogeneous integration technology to address the bandwidth and power consumption challenges by enabling scaling through integration. The shortened chip-to-chip

👥 作者与机构

Mahdi Kashmiri, Ajay Yadav, Jin Namkoong, Behrooz Nakhkoob, Tony Kao, Shen Shen, Vaibhav Pandey, Kuan-Chang Chen, Jinho Han, Sudheer Gaddam,

Shayan Kazemkhani, Sang Young Kim, Simar Maangat, Bo Nguyen, Mike Robinson, Hiva Hedayati Broadcom, San Jose, CA Abstract A 6

分类:Wireline I/O · 年份:ISSCC 2026