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本文提出了一种用于800GbE/1.6TbE标准的224Gb/s/线单端PAM-4收发器前端，通过29dB均衡能力解决了高速长距离传输中的信号完整性挑战。该设计采用单端架构以降低功耗和面积，适用于下一代数据中心和AI系统的高速互连。
Taiyang Fan1, Hongchang Qiao1, Wentao Zhou1, Hongzhi Wu1, Liping Zhong1, Patrick Yin Chiang2, Quan Pan1 Southern University of Science and Technology, Shenzhen, China Fudan University, Shanghai, China 1 2 With the exponential growth of artificial intelligence systems and cloud computing, nextgeneration wireline transceivers are aiming for data rates of 800GbE/1.6TbE, requiring 224Gb/s per lane. Potential 224Gb/s long-reach (LR) solutions [1] include: 1) ADC/DSPbased schemes; 2) PAM-6/PAM-8/OFDM modulation schemes; or 3) PAM-4 retimers with embedded CDRs and equalizers. While all of the above schemes are based on differential signaling, there has been recent interest in single-ended schemes, such as 2D/3D interposer, UCIe, or memory [2, 3, 4]. Compared to differential signaling schemes, single-ended systems can achieve doubled pin efficiency and higher-density IOs. For example, state-of-the-art single-ended links from [4] achieve excellent energy/bit and
Xiongshi Luo1, Xuewei You1, Zhenghao Li1, Hamed Mosalam1, Dongfan Xu1,