A 37.8dB Channel Loss 0.6µs Lock Time CDR with Flash Frequency Acquisition in 5nm FinFET

📋 论文概要

本文提出了一种在高信道损耗下实现快速锁定的时钟数据恢复（CDR）电路，采用Flash频率获取技术，在5nm FinFET工艺中实现了37.8dB信道损耗和0.6µs锁定时间。解决了传统CDR在高损耗下因缺乏先验均衡而难以锁定至大幅频率偏移数据的问题。

💡 主要创新点

• 提出Flash频率获取技术，可在无预先信道均衡的情况下实现高信道损耗下的频率锁定。
• 实现0.6µs极快锁定时间，显著提升CDR在高速SerDes中的响应速度。
• 在5nm FinFET先进工艺中验证，支持37.8dB信道损耗，适应高损耗链路需求。

🏷 关键词

📄 原文摘要

High-speed SerDes is accompanied by high channel loss. Channel loss is usually compensated by transmitter feed-forward equalization (FFE), receiver continuous time linear equalization (CTLE), and receiver decision-feedback equalization (DFE). However, the FFE, CTLE, and DFE can only adjust compensation strength after the CDR is locked. Without well-compensated channel loss, it is difficult for a CDR to lock to input data with significant frequency offset. Several frequency detection techniques are presented in [1-3], but the effect of channel loss on the behavior of CDR locking is less addressed. Achieving fast lock time under high channel loss is a challenge for CDR circuit design. In [3], a stochastic PFD weights three consecutive patterns, data-edge-data, to obtain frequency information. However, the calculated pattern weighting may vary with different channel losses. Moreover, it can only obtain the sign of the frequency offset as a

👥 作者与机构

Chien-Kai Kao, Shih-Che Hung, Tse-Hsien Yeh, Chen-Yu Hsiao

MediaTek, Hsinchu, Taiwan