A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm the selected FFE setting, with proper shift operations involved. This approach minimizes the area and power overhead for the FFE multiplexing, while still covering a sufficient range of configurations for representative channels.

📋 论文概要

提出了一种采用3+1混合FFE抽头的100Gb/s PAM-8发射机，在40nm工艺下实现1.6Vppd高摆幅输出，解决了低工艺节点下PAM-8驱动器设计难题。

💡 主要创新点

• 采用3+1混合FFE抽头架构，在40nm工艺下实现高摆幅PAM-8输出
• 针对PAM-8驱动器中过多输出切片的问题，提出新的输出多路复用技术

🏷 关键词

📄 原文摘要

Hyunwoo Im, Taeho Shin, Jaeduk Han The FIR controller output and the N-bit shifted MSB signals are further upconverted by the following ten 8:4 serializers, producing a 40-bit data stream (TA4, TB4, and TC4 for the normal taps, and TAUX4 for the aux tap) for the final retiming, 4:1 serialization, and output driving operations (Fig. 6.8.4). Despite the relatively low transit frequency of 40nm transistors, the output multiplexing technique utilized by PAM-4 transmitter designs in planar technologies [4-5] is not applicable to the PAM-8 driver due to its excessive number of output slices. Instead, the final 4-to-1 serialization operations are performed separately before the output driving, by utilizing high-speed pulse generation and singlestack multiplexing [2] to avoid stacked transistors at the critical node (4:1 serializer output), similar to [2]. The high-speed pulse generators are composed of dynamic

👥 作者与机构

Jeonghyu Yang*, Eunji Song*, Seungwook Hong, Dongjun Lee, Sangwan Lee,