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ISSCC 2025Session 7 · ULTRA-HIGH-SPEED WIRELINEWireline I/O12nm CMOS

A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS

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📋 论文概要

本文提出了一种在12nm CMOS工艺下实现的224Gb/s超短距接收机,采用基于分片的连续时间线性均衡器和基于相位插值的时钟发生器,解决了在高数据率下CTLE带宽和采样频率的挑战,实现了1.11pJ/b的能效。

💡 主要创新点

核心指标
1.11pJ/b @ 224Gb/s
工艺节点
12nm CMOS
重要性
发表年份
ISSCC 2025

🏷 关键词

超短距接收机连续时间线性均衡器相位插值时钟发生器能效224Gb/s

📄 原文摘要

Integrated Circuits, Beijing, China 1 2 Over the past few decades, process scaling and architecture advancements have led to an exponential increase in transceiver data rates. Recently, 224Gb/s DSP-based receivers (RXs) targeting long-reach electrical and optical transmission have been demonstrated [1-3]. For extra-short reach (XSR) communication at 112Gb/s, analog RXs employing continuoustime linear equalizers (CTLEs) and quarter-rate slicers have shown superior energy efficiency [4-5]. However, doubling CTLE bandwidth and sampling frequency is challenging, particularly when the power and area are limited. This paper presents a 224Gb/s XSR RX that overcomes these challenges using a slice-based CTLE and a PI-based eight-phase clock

👥 作者与机构

Bingyi Ye1,2, Tianchen Ye1, Tianyuan Zhong1, Zhiwen Huang1, Lei Shen1,

Boyang Zhang1, Dunshan Yu1, Yandong He1, Weixin Gai1,3 Peking University, Beijing, China East China Normal University, Shanghai, China 3 Beijing Advanced Innovation Center for

分类:Wireline I/O · 年份:ISSCC 2025