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该论文提出了一种基于DAC的224Gb/s发射机，支持PAM-4和PAM-6调制，采用3nm FinFET工艺，实现了低于pJ/b的能效，满足了800Gb/1.6Tb以太网对单lane速率超过200Gb/s的需求。
Dovid Gottesman1, Daljeet Kumar2, Zvi Marcus1, Yeshayahu Horwitz1, Sagi Zalcman1, Jihwan Kim3, Sandipan Kundu3, Ilia Radashkevich1, Yoav Segal1, Dror Lazar1, Udi Virobnik1, Mike Peng Li4, Ariel Cohen1 Intel, Jerusalem, Israel Intel, Bangalore, India 3 Intel, Hillsboro, OR 4 Intel, San Jose, CA 1 2 As the 800Gb/1.6Tb Ethernet ecosystem develops, a need for single-lane interface speeds beyond 200Gb/s arises. With the first 224Gb/s transmitter and receiver architectures demonstrated in [1] and [2], required energy efficiency per bit and flexibility of silicon proven 112Gb/s designs [3-5] have yet to be reached. Doubling the data-rate puts stringent challenges on the circuit design due to the extra analog bandwidth required, together with the necessary improvement of both random and deterministic jitter performance. This article describes a 224Gb/s transmitter based on a 7b DAC driver (4b binary, 3b thermometer-coded) with 9-tap FFE capable of both PAM-4 and PAM-6
Marco Cusmai1, Noam Familia1, Elad Kuperberg1, Mohammad Nashash1,